1 /*
2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file configuration macros for riscv SOCs supporting the riscv
9  *       privileged architecture specification
10  */
11 
12 #ifndef __SOC_COMMON_H_
13 #define __SOC_COMMON_H_
14 
15 #include "chip_chipregs.h"
16 
17 #ifndef _ASMLANGUAGE
18 
19 #ifdef CONFIG_HAS_ITE_INTC
20 /*
21  * Save current interrupt state of soc-level into ier_setting[] with
22  * disabling interrupt.
23  */
24 void ite_intc_save_and_disable_interrupts(void);
25 /* Restore interrupt state of soc-level from ier_setting[], use with care. */
26 void ite_intc_restore_interrupts(void);
27 
28 extern void ite_intc_irq_enable(unsigned int irq);
29 extern void ite_intc_irq_disable(unsigned int irq);
30 extern uint8_t ite_intc_get_irq_num(void);
31 extern int ite_intc_irq_is_enable(unsigned int irq);
32 extern void ite_intc_irq_polarity_set(unsigned int irq, unsigned int flags);
33 extern void ite_intc_isr_clear(unsigned int irq);
34 void ite_intc_init(void);
35 bool ite_intc_no_irq(void);
36 #endif /* CONFIG_HAS_ITE_INTC */
37 
38 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
39 void timer_5ms_one_shot(void);
40 #endif
41 
42 uint32_t chip_get_pll_freq(void);
43 void chip_pll_ctrl(enum chip_pll_mode mode);
44 void riscv_idle(enum chip_pll_mode mode, unsigned int key);
45 
46 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
47 void chip_permit_idle(void);
48 void chip_block_idle(void);
49 bool cpu_idle_not_allowed(void);
50 #endif
51 
52 #endif /* !_ASMLANGUAGE */
53 
54 #endif /* __SOC_COMMON_H_ */
55