1 /**
2 ******************************************************************************
3 * @file system_stm32wbxx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32wbxx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 8
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * PLLSAI1_P | NA
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_Q | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_R | NA
55 *-----------------------------------------------------------------------------
56 * Require 48MHz for USB OTG FS, | Disabled
57 * SDIO and RNG clock |
58 *-----------------------------------------------------------------------------
59 *=============================================================================
60 ******************************************************************************
61 * @attention
62 *
63 * Copyright (c) 2019-2021 STMicroelectronics.
64 * All rights reserved.
65 *
66 * This software is licensed under terms that can be found in the LICENSE file
67 * in the root directory of this software component.
68 * If no LICENSE file comes with this software, it is provided AS-IS.
69 *
70 ******************************************************************************
71 */
72
73 /** @addtogroup CMSIS
74 * @{
75 */
76
77 /** @addtogroup stm32WBxx_system
78 * @{
79 */
80
81 /** @addtogroup stm32WBxx_System_Private_Includes
82 * @{
83 */
84
85 #include "stm32wbxx.h"
86
87 #if !defined (HSE_VALUE)
88 #define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
89 #endif /* HSE_VALUE */
90
91 #if !defined (MSI_VALUE)
92 #define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
93 #endif /* MSI_VALUE */
94
95 #if !defined (HSI_VALUE)
96 #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
97 #endif /* HSI_VALUE */
98
99 #if !defined (LSI_VALUE)
100 #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
101 #endif /* LSI_VALUE */
102
103 #if !defined (LSE_VALUE)
104 #if defined(STM32WB5Mxx)
105 #define LSE_VALUE 32774U /*!< Value of the LSE oscillator in Hz */
106 #else
107 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
108 #endif /* STM32WB5Mxx */
109 #endif /* LSE_VALUE */
110
111 /**
112 * @}
113 */
114
115 /** @addtogroup STM32WBxx_System_Private_TypesDefinitions
116 * @{
117 */
118
119 /**
120 * @}
121 */
122
123 /** @addtogroup STM32WBxx_System_Private_Defines
124 * @{
125 */
126
127 /* Note: Following vector table addresses must be defined in line with linker
128 configuration. */
129 /*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
130 CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
131 at address 0x00 which correspond to automatic remap of boot address selected */
132 /* #define USER_VECT_TAB_ADDRESS */
133 #if defined(USER_VECT_TAB_ADDRESS)
134 /*!< Uncomment this line for user vector table remap in Sram else user remap
135 will be done in Flash. */
136 /* #define VECT_TAB_SRAM */
137 #if defined(VECT_TAB_SRAM)
138 #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
139 This value must be a multiple of 0x200. */
140 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
141 This value must be a multiple of 0x200. */
142 #else
143 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
144 This value must be a multiple of 0x200. */
145 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
146 This value must be a multiple of 0x200. */
147 #endif /* VECT_TAB_SRAM */
148 #endif /* USER_VECT_TAB_ADDRESS */
149
150 /**
151 * @}
152 */
153
154 /** @addtogroup STM32WBxx_System_Private_Macros
155 * @{
156 */
157
158 /**
159 * @}
160 */
161
162 /** @addtogroup STM32WBxx_System_Private_Variables
163 * @{
164 */
165 /* The SystemCoreClock variable is updated in three ways:
166 1) by calling CMSIS function SystemCoreClockUpdate()
167 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
168 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
169 Note: If you use this function to configure the system clock; then there
170 is no need to call the 2 first functions listed above, since SystemCoreClock
171 variable is updated automatically.
172 */
173 uint32_t SystemCoreClock = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
174
175 const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
176
177 const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
178
179 const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
180 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL
181 }; /* 0UL values are incorrect cases */
182
183 #if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB1Mxx)
184 const uint32_t SmpsPrescalerTable[4UL][6UL] = {{1UL, 3UL, 2UL, 2UL, 1UL, 2UL}, \
185 {2UL, 6UL, 4UL, 3UL, 2UL, 4UL}, \
186 {4UL, 12UL, 8UL, 6UL, 4UL, 8UL}, \
187 {4UL, 12UL, 8UL, 6UL, 4UL, 8UL}
188 };
189 #endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx || STM32WB15xx || STM32WB1Mxx */
190
191 /**
192 * @}
193 */
194
195 /** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
196 * @{
197 */
198
199 /**
200 * @}
201 */
202
203 /** @addtogroup STM32WBxx_System_Private_Functions
204 * @{
205 */
206
207 /**
208 * @brief Setup the microcontroller system.
209 * @param None
210 * @retval None
211 */
SystemInit(void)212 void SystemInit(void)
213 {
214 #if defined(USER_VECT_TAB_ADDRESS)
215 /* Configure the Vector Table location add offset address ------------------*/
216 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
217 #endif /* USER_VECT_TAB_ADDRESS */
218
219 /* FPU settings ------------------------------------------------------------*/
220 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
221 SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
222 #endif /* FPU */
223
224 /* Reset the RCC clock configuration to the default reset state ------------*/
225 /* Set MSION bit */
226 RCC->CR |= RCC_CR_MSION;
227
228 /* Reset CFGR register */
229 RCC->CFGR = 0x00070000U;
230
231 /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
232 RCC->CR &= (uint32_t)0xFAF6FEFBU;
233
234 /*!< Reset LSI1 and LSI2 bits */
235 RCC->CSR &= (uint32_t)0xFFFFFFFAU;
236
237 /*!< Reset HSI48ON bit */
238 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
239
240 /* Reset PLLCFGR register */
241 RCC->PLLCFGR = 0x22041000U;
242
243 #if defined(STM32WB55xx) || defined(STM32WB5Mxx)
244 /* Reset PLLSAI1CFGR register */
245 RCC->PLLSAI1CFGR = 0x22041000U;
246 #endif /* STM32WB55xx || STM32WB5Mxx */
247
248 /* Reset HSEBYP bit */
249 RCC->CR &= 0xFFFBFFFFU;
250
251 /* Disable all interrupts */
252 RCC->CIER = 0x00000000;
253 }
254
255 /**
256 * @brief Update SystemCoreClock variable according to Clock Register Values.
257 * The SystemCoreClock variable contains the core clock (HCLK), it can
258 * be used by the user application to setup the SysTick timer or configure
259 * other parameters.
260 *
261 * @note Each time the core clock (HCLK) changes, this function must be called
262 * to update SystemCoreClock variable value. Otherwise, any configuration
263 * based on this variable will be incorrect.
264 *
265 * @note - The system frequency computed by this function is not the real
266 * frequency in the chip. It is calculated based on the predefined
267 * constant and the selected clock source:
268 *
269 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
270 *
271 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
272 *
273 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
274 *
275 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
276 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
277 *
278 * (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
279 * 4 MHz) but the real value may vary depending on the variations
280 * in voltage and temperature.
281 *
282 * (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
283 * 16 MHz) but the real value may vary depending on the variations
284 * in voltage and temperature.
285 *
286 * (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
287 * 32 MHz), user has to ensure that HSE_VALUE is same as the real
288 * frequency of the crystal used. Otherwise, this function may
289 * have wrong result.
290 *
291 * - The result of this function could be not correct when using fractional
292 * value for HSE crystal.
293 *
294 * @param None
295 * @retval None
296 */
SystemCoreClockUpdate(void)297 void SystemCoreClockUpdate(void)
298 {
299 uint32_t tmp, msirange, pllvco, pllr, pllsource, pllm;
300
301 /* Get MSI Range frequency--------------------------------------------------*/
302
303 /*MSI frequency range in Hz*/
304 msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
305
306 /* Get SYSCLK source -------------------------------------------------------*/
307 switch (RCC->CFGR & RCC_CFGR_SWS)
308 {
309 case 0x00: /* MSI used as system clock source */
310 SystemCoreClock = msirange;
311 break;
312
313 case 0x04: /* HSI used as system clock source */
314 /* HSI used as system clock source */
315 SystemCoreClock = HSI_VALUE;
316 break;
317
318 case 0x08: /* HSE used as system clock source */
319 SystemCoreClock = HSE_VALUE;
320 break;
321
322 case 0x0C: /* PLL used as system clock source */
323 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
324 SYSCLK = PLL_VCO / PLLR
325 */
326 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
327 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
328
329 if (pllsource == 0x02UL) /* HSI used as PLL clock source */
330 {
331 pllvco = (HSI_VALUE / pllm);
332 }
333 else if (pllsource == 0x03UL) /* HSE used as PLL clock source */
334 {
335 pllvco = (HSE_VALUE / pllm);
336 }
337 else /* MSI used as PLL clock source */
338 {
339 pllvco = (msirange / pllm);
340 }
341
342 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
343 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
344
345 SystemCoreClock = pllvco / pllr;
346 break;
347
348 default:
349 SystemCoreClock = msirange;
350 break;
351 }
352
353 /* Compute HCLK clock frequency --------------------------------------------*/
354 /* Get HCLK1 prescaler */
355 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
356
357 /* HCLK clock frequency */
358 SystemCoreClock = SystemCoreClock / tmp;
359 }
360
361
362 /**
363 * @}
364 */
365
366 /**
367 * @}
368 */
369
370 /**
371 * @}
372 */
373
