1 /**
2 ******************************************************************************
3 * @file system_stm32u5xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32u5xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * APB3 Prescaler | 1
41 *-----------------------------------------------------------------------------
42 * PLL1_SRC | No clock
43 *-----------------------------------------------------------------------------
44 * PLL1_M | 1
45 *-----------------------------------------------------------------------------
46 * PLL1_N | 8
47 *-----------------------------------------------------------------------------
48 * PLL1_P | 7
49 *-----------------------------------------------------------------------------
50 * PLL1_Q | 2
51 *-----------------------------------------------------------------------------
52 * PLL1_R | 2
53 *-----------------------------------------------------------------------------
54 * PLL2_SRC | NA
55 *-----------------------------------------------------------------------------
56 * PLL2_M | NA
57 *-----------------------------------------------------------------------------
58 * PLL2_N | NA
59 *-----------------------------------------------------------------------------
60 * PLL2_P | NA
61 *-----------------------------------------------------------------------------
62 * PLL2_Q | NA
63 *-----------------------------------------------------------------------------
64 * PLL2_R | NA
65 *-----------------------------------------------------------------------------
66 * PLL3_SRC | NA
67 *-----------------------------------------------------------------------------
68 * PLL3_M | NA
69 *-----------------------------------------------------------------------------
70 * PLL3_N | NA
71 *-----------------------------------------------------------------------------
72 * PLL3_P | NA
73 *-----------------------------------------------------------------------------
74 * Require 48MHz for USB FS, | Disabled
75 * SDIO and RNG clock |
76 *-----------------------------------------------------------------------------
77 *=============================================================================
78 ******************************************************************************
79 * @attention
80 *
81 * Copyright (c) 2021 STMicroelectronics.
82 * All rights reserved.
83 *
84 * This software is licensed under terms that can be found in the LICENSE file
85 * in the root directory of this software component.
86 * If no LICENSE file comes with this software, it is provided AS-IS.
87 *
88 ******************************************************************************
89 */
90
91 /** @addtogroup CMSIS
92 * @{
93 */
94
95 /** @addtogroup STM32U5xx_system
96 * @{
97 */
98
99 /** @addtogroup STM32U5xx_System_Private_Includes
100 * @{
101 */
102
103 #include "stm32u5xx.h"
104 #include <math.h>
105
106 /**
107 * @}
108 */
109
110 /** @addtogroup STM32U5xx_System_Private_TypesDefinitions
111 * @{
112 */
113
114 /**
115 * @}
116 */
117
118 /** @addtogroup STM32U5xx_System_Private_Defines
119 * @{
120 */
121
122 #if !defined (HSE_VALUE)
123 #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
124 #endif /* HSE_VALUE */
125
126 #if !defined (MSI_VALUE)
127 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
128 #endif /* MSI_VALUE */
129
130 #if !defined (HSI_VALUE)
131 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
132 #endif /* HSI_VALUE */
133
134 /************************* Miscellaneous Configuration ************************/
135 /*!< Uncomment the following line if you need to relocate your vector Table in
136 Internal SRAM. */
137 /* #define VECT_TAB_SRAM */
138 #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
139 This value must be a multiple of 0x200. */
140 /******************************************************************************/
141
142 /**
143 * @}
144 */
145
146 /** @addtogroup STM32U5xx_System_Private_Macros
147 * @{
148 */
149
150 /**
151 * @}
152 */
153
154 /** @addtogroup STM32U5xx_System_Private_Variables
155 * @{
156 */
157 /* The SystemCoreClock variable is updated in three ways:
158 1) by calling CMSIS function SystemCoreClockUpdate()
159 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
160 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
161 Note: If you use this function to configure the system clock; then there
162 is no need to call the 2 first functions listed above, since SystemCoreClock
163 variable is updated automatically.
164 */
165 uint32_t SystemCoreClock = 4000000U;
166
167 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
168 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
169 const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\
170 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U};
171 /**
172 * @}
173 */
174
175 /** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
176 * @{
177 */
178
179 /**
180 * @}
181 */
182
183 /** @addtogroup STM32U5xx_System_Private_Functions
184 * @{
185 */
186
187 /**
188 * @brief Setup the microcontroller system.
189 * @param None
190 * @retval None
191 */
192
SystemInit(void)193 void SystemInit(void)
194 {
195 /* FPU settings ------------------------------------------------------------*/
196 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
197 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
198 #endif
199
200 /* Reset the RCC clock configuration to the default reset state ------------*/
201 /* Set MSION bit */
202 RCC->CR = RCC_CR_MSISON;
203
204 /* Reset CFGR register */
205 RCC->CFGR1 = 0U;
206 RCC->CFGR2 = 0U;
207 RCC->CFGR3 = 0U;
208
209 /* Reset HSEON, CSSON , HSION, PLLxON bits */
210 RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
211
212 /* Reset PLLCFGR register */
213 RCC->PLL1CFGR = 0U;
214
215 /* Reset HSEBYP bit */
216 RCC->CR &= ~(RCC_CR_HSEBYP);
217
218 /* Disable all interrupts */
219 RCC->CIER = 0U;
220
221 /* Configure the Vector Table location add offset address ------------------*/
222 #ifdef VECT_TAB_SRAM
223 SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
224 #else
225 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
226 #endif
227 }
228
229 /**
230 * @brief Update SystemCoreClock variable according to Clock Register Values.
231 * The SystemCoreClock variable contains the core clock (HCLK), it can
232 * be used by the user application to setup the SysTick timer or configure
233 * other parameters.
234 *
235 * @note Each time the core clock (HCLK) changes, this function must be called
236 * to update SystemCoreClock variable value. Otherwise, any configuration
237 * based on this variable will be incorrect.
238 *
239 * @note - The system frequency computed by this function is not the real
240 * frequency in the chip. It is calculated based on the predefined
241 * constant and the selected clock source:
242 *
243 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
244 *
245 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
246 *
247 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
248 *
249 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
250 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
251 *
252 * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
253 * 4 MHz) but the real value may vary depending on the variations
254 * in voltage and temperature.
255 *
256 * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
257 * 16 MHz) but the real value may vary depending on the variations
258 * in voltage and temperature.
259 *
260 * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
261 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
262 * frequency of the crystal used. Otherwise, this function may
263 * have wrong result.
264 *
265 * - The result of this function could be not correct when using fractional
266 * value for HSE crystal.
267 *
268 * @param None
269 * @retval None
270 */
SystemCoreClockUpdate(void)271 void SystemCoreClockUpdate(void)
272 {
273 uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
274 float_t fracn1, pllvco;
275
276 /* Get MSI Range frequency--------------------------------------------------*/
277 if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
278 {
279 /* MSISRANGE from RCC_CSR applies */
280 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
281 }
282 else
283 {
284 /* MSIRANGE from RCC_CR applies */
285 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
286 }
287
288 /*MSI frequency range in HZ*/
289 msirange = MSIRangeTable[msirange];
290
291 /* Get SYSCLK source -------------------------------------------------------*/
292 switch (RCC->CFGR1 & RCC_CFGR1_SWS)
293 {
294 case 0x00: /* MSI used as system clock source */
295 SystemCoreClock = msirange;
296 break;
297
298 case 0x04: /* HSI used as system clock source */
299 SystemCoreClock = HSI_VALUE;
300 break;
301
302 case 0x08: /* HSE used as system clock source */
303 SystemCoreClock = HSE_VALUE;
304 break;
305
306 case 0x0C: /* PLL used as system clock source */
307 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
308 SYSCLK = PLL_VCO / PLLR
309 */
310 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
311 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
312 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
313 fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
314
315 switch (pllsource)
316 {
317 case 0x00: /* No clock sent to PLL*/
318 pllvco = (float_t)0U;
319 break;
320
321 case 0x02: /* HSI used as PLL clock source */
322 pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
323 break;
324
325 case 0x03: /* HSE used as PLL clock source */
326 pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
327 break;
328
329 default: /* MSI used as PLL clock source */
330 pllvco = ((float_t)msirange / (float_t)pllm);
331 break;
332 }
333
334 pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
335 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
336 SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
337 break;
338
339 default:
340 SystemCoreClock = msirange;
341 break;
342 }
343 /* Compute HCLK clock frequency --------------------------------------------*/
344 /* Get HCLK prescaler */
345 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
346 /* HCLK clock frequency */
347 SystemCoreClock >>= tmp;
348 }
349
350
351 /**
352 * @}
353 */
354
355 /**
356 * @}
357 */
358
359 /**
360 * @}
361 */
362
363
