1 /**
2 ******************************************************************************
3 * @file system_stm32g4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32g4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the HSI (16 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | HSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 16000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 16000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 16
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * Require 48MHz for RNG | Disabled
51 *-----------------------------------------------------------------------------
52 *=============================================================================
53 ******************************************************************************
54 * @attention
55 *
56 * Copyright (c) 2019 STMicroelectronics.
57 * All rights reserved.
58 *
59 * This software is licensed under terms that can be found in the LICENSE file
60 * in the root directory of this software component.
61 * If no LICENSE file comes with this software, it is provided AS-IS.
62 *
63 ******************************************************************************
64 */
65
66 /** @addtogroup CMSIS
67 * @{
68 */
69
70 /** @addtogroup stm32g4xx_system
71 * @{
72 */
73
74 /** @addtogroup STM32G4xx_System_Private_Includes
75 * @{
76 */
77
78 #include "stm32g4xx.h"
79
80 #if !defined (HSE_VALUE)
81 #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
82 #endif /* HSE_VALUE */
83
84 #if !defined (HSI_VALUE)
85 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
86 #endif /* HSI_VALUE */
87
88 /**
89 * @}
90 */
91
92 /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
93 * @{
94 */
95
96 /**
97 * @}
98 */
99
100 /** @addtogroup STM32G4xx_System_Private_Defines
101 * @{
102 */
103
104 /************************* Miscellaneous Configuration ************************/
105 /* Note: Following vector table addresses must be defined in line with linker
106 configuration. */
107 /*!< Uncomment the following line if you need to relocate the vector table
108 anywhere in Flash or Sram, else the vector table is kept at the automatic
109 remap of boot address selected */
110 /* #define USER_VECT_TAB_ADDRESS */
111
112 #if defined(USER_VECT_TAB_ADDRESS)
113 /*!< Uncomment the following line if you need to relocate your vector Table
114 in Sram else user remap will be done in Flash. */
115 /* #define VECT_TAB_SRAM */
116 #if defined(VECT_TAB_SRAM)
117 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
118 This value must be a multiple of 0x200. */
119 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
120 This value must be a multiple of 0x200. */
121 #else
122 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
123 This value must be a multiple of 0x200. */
124 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
125 This value must be a multiple of 0x200. */
126 #endif /* VECT_TAB_SRAM */
127 #endif /* USER_VECT_TAB_ADDRESS */
128 /******************************************************************************/
129 /**
130 * @}
131 */
132
133 /** @addtogroup STM32G4xx_System_Private_Macros
134 * @{
135 */
136
137 /**
138 * @}
139 */
140
141 /** @addtogroup STM32G4xx_System_Private_Variables
142 * @{
143 */
144 /* The SystemCoreClock variable is updated in three ways:
145 1) by calling CMSIS function SystemCoreClockUpdate()
146 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
147 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
148 Note: If you use this function to configure the system clock; then there
149 is no need to call the 2 first functions listed above, since SystemCoreClock
150 variable is updated automatically.
151 */
152 uint32_t SystemCoreClock = HSI_VALUE;
153
154 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
155 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
156
157 /**
158 * @}
159 */
160
161 /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
162 * @{
163 */
164
165 /**
166 * @}
167 */
168
169 /** @addtogroup STM32G4xx_System_Private_Functions
170 * @{
171 */
172
173 /**
174 * @brief Setup the microcontroller system.
175 * @param None
176 * @retval None
177 */
178
SystemInit(void)179 void SystemInit(void)
180 {
181 /* FPU settings ------------------------------------------------------------*/
182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
183 SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
184 #endif
185
186 /* Configure the Vector Table location add offset address ------------------*/
187 #if defined(USER_VECT_TAB_ADDRESS)
188 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
189 #endif /* USER_VECT_TAB_ADDRESS */
190 }
191
192 /**
193 * @brief Update SystemCoreClock variable according to Clock Register Values.
194 * The SystemCoreClock variable contains the core clock (HCLK), it can
195 * be used by the user application to setup the SysTick timer or configure
196 * other parameters.
197 *
198 * @note Each time the core clock (HCLK) changes, this function must be called
199 * to update SystemCoreClock variable value. Otherwise, any configuration
200 * based on this variable will be incorrect.
201 *
202 * @note - The system frequency computed by this function is not the real
203 * frequency in the chip. It is calculated based on the predefined
204 * constant and the selected clock source:
205 *
206 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
207 *
208 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
209 *
210 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
211 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
212 *
213 * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
214 * 16 MHz) but the real value may vary depending on the variations
215 * in voltage and temperature.
216 *
217 * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
218 * 24 MHz), user has to ensure that HSE_VALUE is same as the real
219 * frequency of the crystal used. Otherwise, this function may
220 * have wrong result.
221 *
222 * - The result of this function could be not correct when using fractional
223 * value for HSE crystal.
224 *
225 * @param None
226 * @retval None
227 */
SystemCoreClockUpdate(void)228 void SystemCoreClockUpdate(void)
229 {
230 uint32_t tmp, pllvco, pllr, pllsource, pllm;
231
232 /* Get SYSCLK source -------------------------------------------------------*/
233 switch (RCC->CFGR & RCC_CFGR_SWS)
234 {
235 case 0x04: /* HSI used as system clock source */
236 SystemCoreClock = HSI_VALUE;
237 break;
238
239 case 0x08: /* HSE used as system clock source */
240 SystemCoreClock = HSE_VALUE;
241 break;
242
243 case 0x0C: /* PLL used as system clock source */
244 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
245 SYSCLK = PLL_VCO / PLLR
246 */
247 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
248 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
249 if (pllsource == 0x02UL) /* HSI used as PLL clock source */
250 {
251 pllvco = (HSI_VALUE / pllm);
252 }
253 else /* HSE used as PLL clock source */
254 {
255 pllvco = (HSE_VALUE / pllm);
256 }
257 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
258 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
259 SystemCoreClock = pllvco/pllr;
260 break;
261
262 default:
263 break;
264 }
265 /* Compute HCLK clock frequency --------------------------------------------*/
266 /* Get HCLK prescaler */
267 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
268 /* HCLK clock frequency */
269 SystemCoreClock >>= tmp;
270 }
271
272
273 /**
274 * @}
275 */
276
277 /**
278 * @}
279 */
280
281 /**
282 * @}
283 */
284
285
286
