1 /**
2 ******************************************************************************
3 * @file system_stm32f3xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6 *
7 * 1. This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32f3xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * 3. This file configures the system clock as follows:
26 *=============================================================================
27 * Supported STM32F3xx device
28 *-----------------------------------------------------------------------------
29 * System Clock source | HSI
30 *-----------------------------------------------------------------------------
31 * SYSCLK(Hz) | 8000000
32 *-----------------------------------------------------------------------------
33 * HCLK(Hz) | 8000000
34 *-----------------------------------------------------------------------------
35 * AHB Prescaler | 1
36 *-----------------------------------------------------------------------------
37 * APB2 Prescaler | 1
38 *-----------------------------------------------------------------------------
39 * APB1 Prescaler | 1
40 *-----------------------------------------------------------------------------
41 * USB Clock | DISABLE
42 *-----------------------------------------------------------------------------
43 *=============================================================================
44 ******************************************************************************
45 * @attention
46 *
47 * Copyright (c) 2016 STMicroelectronics.
48 * All rights reserved.
49 *
50 * This software is licensed under terms that can be found in the LICENSE file
51 * in the root directory of this software component.
52 * If no LICENSE file comes with this software, it is provided AS-IS.
53 *
54 ******************************************************************************
55 */
56
57 /** @addtogroup CMSIS
58 * @{
59 */
60
61 /** @addtogroup stm32f3xx_system
62 * @{
63 */
64
65 /** @addtogroup STM32F3xx_System_Private_Includes
66 * @{
67 */
68
69 #include "stm32f3xx.h"
70
71 /**
72 * @}
73 */
74
75 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
76 * @{
77 */
78
79 /**
80 * @}
81 */
82
83 /** @addtogroup STM32F3xx_System_Private_Defines
84 * @{
85 */
86 #if !defined (HSE_VALUE)
87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
88 This value can be provided and adapted by the user application. */
89 #endif /* HSE_VALUE */
90
91 #if !defined (HSI_VALUE)
92 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
93 This value can be provided and adapted by the user application. */
94 #endif /* HSI_VALUE */
95
96 /* Note: Following vector table addresses must be defined in line with linker
97 configuration. */
98 /*!< Uncomment the following line if you need to relocate the vector table
99 anywhere in Flash or Sram, else the vector table is kept at the automatic
100 remap of boot address selected */
101 /* #define USER_VECT_TAB_ADDRESS */
102
103 #if defined(USER_VECT_TAB_ADDRESS)
104 /*!< Uncomment the following line if you need to relocate your vector Table
105 in Sram else user remap will be done in Flash. */
106 /* #define VECT_TAB_SRAM */
107 #if defined(VECT_TAB_SRAM)
108 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
109 This value must be a multiple of 0x200. */
110 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
111 This value must be a multiple of 0x200. */
112 #else
113 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
114 This value must be a multiple of 0x200. */
115 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
116 This value must be a multiple of 0x200. */
117 #endif /* VECT_TAB_SRAM */
118 #endif /* USER_VECT_TAB_ADDRESS */
119
120 /******************************************************************************/
121 /**
122 * @}
123 */
124
125 /** @addtogroup STM32F3xx_System_Private_Macros
126 * @{
127 */
128
129 /**
130 * @}
131 */
132
133 /** @addtogroup STM32F3xx_System_Private_Variables
134 * @{
135 */
136 /* This variable is updated in three ways:
137 1) by calling CMSIS function SystemCoreClockUpdate()
138 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
139 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
140 Note: If you use this function to configure the system clock there is no need to
141 call the 2 first functions listed above, since SystemCoreClock variable is
142 updated automatically.
143 */
144 uint32_t SystemCoreClock = 8000000;
145
146 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
147 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
148
149 /**
150 * @}
151 */
152
153 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
154 * @{
155 */
156
157 /**
158 * @}
159 */
160
161 /** @addtogroup STM32F3xx_System_Private_Functions
162 * @{
163 */
164
165 /**
166 * @brief Setup the microcontroller system
167 * @param None
168 * @retval None
169 */
SystemInit(void)170 void SystemInit(void)
171 {
172 /* FPU settings --------------------------------------------------------------*/
173 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
174 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
175 #endif
176
177 /* Configure the Vector Table location -------------------------------------*/
178 #if defined(USER_VECT_TAB_ADDRESS)
179 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
180 #endif /* USER_VECT_TAB_ADDRESS */
181 }
182
183 /**
184 * @brief Update SystemCoreClock variable according to Clock Register Values.
185 * The SystemCoreClock variable contains the core clock (HCLK), it can
186 * be used by the user application to setup the SysTick timer or configure
187 * other parameters.
188 *
189 * @note Each time the core clock (HCLK) changes, this function must be called
190 * to update SystemCoreClock variable value. Otherwise, any configuration
191 * based on this variable will be incorrect.
192 *
193 * @note - The system frequency computed by this function is not the real
194 * frequency in the chip. It is calculated based on the predefined
195 * constant and the selected clock source:
196 *
197 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
198 *
199 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
200 *
201 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
202 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
203 *
204 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
205 * 8 MHz) but the real value may vary depending on the variations
206 * in voltage and temperature.
207 *
208 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
209 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
210 * frequency of the crystal used. Otherwise, this function may
211 * have wrong result.
212 *
213 * - The result of this function could be not correct when using fractional
214 * value for HSE crystal.
215 *
216 * @param None
217 * @retval None
218 */
SystemCoreClockUpdate(void)219 void SystemCoreClockUpdate (void)
220 {
221 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
222
223 /* Get SYSCLK source -------------------------------------------------------*/
224 tmp = RCC->CFGR & RCC_CFGR_SWS;
225
226 switch (tmp)
227 {
228 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
229 SystemCoreClock = HSI_VALUE;
230 break;
231 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
232 SystemCoreClock = HSE_VALUE;
233 break;
234 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
235 /* Get PLL clock source and multiplication factor ----------------------*/
236 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
237 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
238 pllmull = ( pllmull >> 18) + 2;
239
240 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
241 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
242 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
243 {
244 /* HSE oscillator clock selected as PREDIV1 clock entry */
245 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
246 }
247 else
248 {
249 /* HSI oscillator clock selected as PREDIV1 clock entry */
250 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
251 }
252 #else
253 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
254 {
255 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
256 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
257 }
258 else
259 {
260 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
261 /* HSE oscillator clock selected as PREDIV1 clock entry */
262 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
263 }
264 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
265 break;
266 default: /* HSI used as system clock */
267 SystemCoreClock = HSI_VALUE;
268 break;
269 }
270 /* Compute HCLK clock frequency ----------------*/
271 /* Get HCLK prescaler */
272 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
273 /* HCLK clock frequency */
274 SystemCoreClock >>= tmp;
275 }
276
277 /**
278 * @}
279 */
280
281 /**
282 * @}
283 */
284
285 /**
286 * @}
287 */
288
