1 /**
2 ******************************************************************************
3 * @file system_stm32f2xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32f2xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 ******************************************************************************
22 * @attention
23 *
24 * Copyright (c) 2017-2021 STMicroelectronics.
25 * All rights reserved.
26 *
27 * This software is licensed under terms that can be found in the LICENSE file
28 * in the root directory of this software component.
29 * If no LICENSE file comes with this software, it is provided AS-IS.
30 *
31 ******************************************************************************
32 */
33
34 /** @addtogroup CMSIS
35 * @{
36 */
37
38 /** @addtogroup stm32f2xx_system
39 * @{
40 */
41
42 /** @addtogroup STM32F2xx_System_Private_Includes
43 * @{
44 */
45
46 #include "stm32f2xx.h"
47
48 #if !defined (HSE_VALUE)
49 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
50 #endif /* HSE_VALUE */
51
52 #if !defined (HSI_VALUE)
53 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
54 #endif /* HSI_VALUE */
55
56 /**
57 * @}
58 */
59
60 /** @addtogroup STM32F2xx_System_Private_TypesDefinitions
61 * @{
62 */
63
64 /**
65 * @}
66 */
67
68 /** @addtogroup STM32F2xx_System_Private_Defines
69 * @{
70 */
71 /************************* Miscellaneous Configuration ************************/
72 /*!< Uncomment the following line if you need to use external SRAM mounted
73 on STM322xG_EVAL board as data memory */
74 /* #define DATA_IN_ExtSRAM */
75
76 /* Note: Following vector table addresses must be defined in line with linker
77 configuration. */
78 /*!< Uncomment the following line if you need to relocate the vector table
79 anywhere in Flash or Sram, else the vector table is kept at the automatic
80 remap of boot address selected */
81 /* #define USER_VECT_TAB_ADDRESS */
82
83 #if defined(USER_VECT_TAB_ADDRESS)
84 /*!< Uncomment the following line if you need to relocate your vector Table
85 in Sram else user remap will be done in Flash. */
86 /* #define VECT_TAB_SRAM */
87 #if defined(VECT_TAB_SRAM)
88 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
89 This value must be a multiple of 0x200. */
90 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
91 This value must be a multiple of 0x200. */
92 #else
93 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
94 This value must be a multiple of 0x200. */
95 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
96 This value must be a multiple of 0x200. */
97 #endif /* VECT_TAB_SRAM */
98 #endif /* USER_VECT_TAB_ADDRESS */
99
100 /******************************************************************************/
101
102 /**
103 * @}
104 */
105
106 /** @addtogroup STM32F2xx_System_Private_Macros
107 * @{
108 */
109
110 /**
111 * @}
112 */
113
114 /** @addtogroup STM32F2xx_System_Private_Variables
115 * @{
116 */
117
118 /* This variable can be updated in Three ways :
119 1) by calling CMSIS function SystemCoreClockUpdate()
120 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
121 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
122 Note: If you use this function to configure the system clock; then there
123 is no need to call the 2 first functions listed above, since SystemCoreClock
124 variable is updated automatically.
125 */
126 uint32_t SystemCoreClock = 16000000;
127 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
128 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
129 /**
130 * @}
131 */
132
133 /** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
134 * @{
135 */
136
137 #ifdef DATA_IN_ExtSRAM
138 static void SystemInit_ExtMemCtl(void);
139 #endif /* DATA_IN_ExtSRAM */
140
141 /**
142 * @}
143 */
144
145 /** @addtogroup STM32F2xx_System_Private_Functions
146 * @{
147 */
148
149 /**
150 * @brief Setup the microcontroller system
151 * Initialize the Embedded Flash Interface, the PLL and update the
152 * SystemFrequency variable.
153 * @param None
154 * @retval None
155 */
SystemInit(void)156 void SystemInit(void)
157 {
158 #ifdef DATA_IN_ExtSRAM
159 SystemInit_ExtMemCtl();
160 #endif /* DATA_IN_ExtSRAM */
161
162 /* Configure the Vector Table location -------------------------------------*/
163 #if defined(USER_VECT_TAB_ADDRESS)
164 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
165 #endif /* USER_VECT_TAB_ADDRESS */
166 }
167
168 /**
169 * @brief Update SystemCoreClock variable according to Clock Register Values.
170 * The SystemCoreClock variable contains the core clock (HCLK), it can
171 * be used by the user application to setup the SysTick timer or configure
172 * other parameters.
173 *
174 * @note Each time the core clock (HCLK) changes, this function must be called
175 * to update SystemCoreClock variable value. Otherwise, any configuration
176 * based on this variable will be incorrect.
177 *
178 * @note - The system frequency computed by this function is not the real
179 * frequency in the chip. It is calculated based on the predefined
180 * constant and the selected clock source:
181 *
182 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
183 *
184 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
185 *
186 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
187 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
188 *
189 * (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
190 * 16 MHz) but the real value may vary depending on the variations
191 * in voltage and temperature.
192 *
193 * (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
194 * depends on the application requirements), user has to ensure that HSE_VALUE
195 * is same as the real frequency of the crystal used. Otherwise, this function
196 * may have wrong result.
197 *
198 * - The result of this function could be not correct when using fractional
199 * value for HSE crystal.
200 *
201 * @param None
202 * @retval None
203 */
SystemCoreClockUpdate(void)204 void SystemCoreClockUpdate(void)
205 {
206 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
207
208 /* Get SYSCLK source -------------------------------------------------------*/
209 tmp = RCC->CFGR & RCC_CFGR_SWS;
210
211 switch (tmp)
212 {
213 case 0x00: /* HSI used as system clock source */
214 SystemCoreClock = HSI_VALUE;
215 break;
216 case 0x04: /* HSE used as system clock source */
217 SystemCoreClock = HSE_VALUE;
218 break;
219 case 0x08: /* PLL used as system clock source */
220
221 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
222 SYSCLK = PLL_VCO / PLL_P
223 */
224 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
225 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
226
227 if (pllsource != 0)
228 {
229 /* HSE used as PLL clock source */
230 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
231 }
232 else
233 {
234 /* HSI used as PLL clock source */
235 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
236 }
237
238 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
239 SystemCoreClock = pllvco/pllp;
240 break;
241 default:
242 SystemCoreClock = HSI_VALUE;
243 break;
244 }
245 /* Compute HCLK frequency --------------------------------------------------*/
246 /* Get HCLK prescaler */
247 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
248 /* HCLK frequency */
249 SystemCoreClock >>= tmp;
250 }
251
252 #ifdef DATA_IN_ExtSRAM
253 /**
254 * @brief Setup the external memory controller.
255 * Called in startup_stm32f2xx.s before jump to main.
256 * This function configures the external SRAM mounted on STM322xG_EVAL board
257 * This SRAM will be used as program data memory (including heap and stack).
258 * @param None
259 * @retval None
260 */
SystemInit_ExtMemCtl(void)261 void SystemInit_ExtMemCtl(void)
262 {
263 __IO uint32_t tmp = 0x00;
264
265 /*-- GPIOs Configuration -----------------------------------------------------*/
266 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
267 RCC->AHB1ENR |= 0x00000078;
268 /* Delay after an RCC peripheral clock enabling */
269 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
270 (void)(tmp);
271
272 /* Connect PDx pins to FSMC Alternate function */
273 GPIOD->AFR[0] = 0x00CCC0CC;
274 GPIOD->AFR[1] = 0xCCCCCCCC;
275 /* Configure PDx pins in Alternate function mode */
276 GPIOD->MODER = 0xAAAA0A8A;
277 /* Configure PDx pins speed to 100 MHz */
278 GPIOD->OSPEEDR = 0xFFFF0FCF;
279 /* Configure PDx pins Output type to push-pull */
280 GPIOD->OTYPER = 0x00000000;
281 /* No pull-up, pull-down for PDx pins */
282 GPIOD->PUPDR = 0x00000000;
283
284 /* Connect PEx pins to FSMC Alternate function */
285 GPIOE->AFR[0] = 0xC00CC0CC;
286 GPIOE->AFR[1] = 0xCCCCCCCC;
287 /* Configure PEx pins in Alternate function mode */
288 GPIOE->MODER = 0xAAAA828A;
289 /* Configure PEx pins speed to 100 MHz */
290 GPIOE->OSPEEDR = 0xFFFFC3CF;
291 /* Configure PEx pins Output type to push-pull */
292 GPIOE->OTYPER = 0x00000000;
293 /* No pull-up, pull-down for PEx pins */
294 GPIOE->PUPDR = 0x00000000;
295
296 /* Connect PFx pins to FSMC Alternate function */
297 GPIOF->AFR[0] = 0x00CCCCCC;
298 GPIOF->AFR[1] = 0xCCCC0000;
299 /* Configure PFx pins in Alternate function mode */
300 GPIOF->MODER = 0xAA000AAA;
301 /* Configure PFx pins speed to 100 MHz */
302 GPIOF->OSPEEDR = 0xFF000FFF;
303 /* Configure PFx pins Output type to push-pull */
304 GPIOF->OTYPER = 0x00000000;
305 /* No pull-up, pull-down for PFx pins */
306 GPIOF->PUPDR = 0x00000000;
307
308 /* Connect PGx pins to FSMC Alternate function */
309 GPIOG->AFR[0] = 0x00CCCCCC;
310 GPIOG->AFR[1] = 0x000000C0;
311 /* Configure PGx pins in Alternate function mode */
312 GPIOG->MODER = 0x00085AAA;
313 /* Configure PGx pins speed to 100 MHz */
314 GPIOG->OSPEEDR = 0x000CAFFF;
315 /* Configure PGx pins Output type to push-pull */
316 GPIOG->OTYPER = 0x00000000;
317 /* No pull-up, pull-down for PGx pins */
318 GPIOG->PUPDR = 0x00000000;
319
320 /*--FSMC Configuration -------------------------------------------------------*/
321 /* Enable the FSMC interface clock */
322 RCC->AHB3ENR |= 0x00000001;
323
324 /* Configure and enable Bank1_SRAM2 */
325 FSMC_Bank1->BTCR[2] = 0x00001011;
326 FSMC_Bank1->BTCR[3] = 0x00000201;
327 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
328 }
329 #endif /* DATA_IN_ExtSRAM */
330
331
332 /**
333 * @}
334 */
335
336 /**
337 * @}
338 */
339
340 /**
341 * @}
342 */
343
