1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #define MODEM_CLKRST_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x0) 16 /* MODEM_CLKRST_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 17 /*description: .*/ 18 #define MODEM_CLKRST_CLK_EN (BIT(0)) 19 #define MODEM_CLKRST_CLK_EN_M (BIT(0)) 20 #define MODEM_CLKRST_CLK_EN_V 0x1 21 #define MODEM_CLKRST_CLK_EN_S 0 22 23 #define MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x4) 24 /* MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */ 25 /*description: .*/ 26 #define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM 0x000000FF 27 #define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_M ((MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V)<<(MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S)) 28 #define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_V 0xFF 29 #define MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S 4 30 /* MODEM_CLKRST_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ 31 /*description: .*/ 32 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K (BIT(3)) 33 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_M (BIT(3)) 34 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_V 0x1 35 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S 3 36 /* MODEM_CLKRST_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 37 /*description: .*/ 38 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL (BIT(2)) 39 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL_M (BIT(2)) 40 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL_V 0x1 41 #define MODEM_CLKRST_LP_TIMER_SEL_XTAL_S 2 42 /* MODEM_CLKRST_LP_TIMER_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */ 43 /*description: .*/ 44 #define MODEM_CLKRST_LP_TIMER_SEL_8M (BIT(1)) 45 #define MODEM_CLKRST_LP_TIMER_SEL_8M_M (BIT(1)) 46 #define MODEM_CLKRST_LP_TIMER_SEL_8M_V 0x1 47 #define MODEM_CLKRST_LP_TIMER_SEL_8M_S 1 48 /* MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ 49 /*description: .*/ 50 #define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW (BIT(0)) 51 #define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_M (BIT(0)) 52 #define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_V 0x1 53 #define MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S 0 54 55 #define MODEM_CLKRST_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x8) 56 /* MODEM_CLKRST_COEX_LPCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h0 ; */ 57 /*description: .*/ 58 #define MODEM_CLKRST_COEX_LPCLK_DIV_NUM 0x000000FF 59 #define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_M ((MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V)<<(MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S)) 60 #define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_V 0xFF 61 #define MODEM_CLKRST_COEX_LPCLK_DIV_NUM_S 4 62 /* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ 63 /*description: .*/ 64 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K (BIT(3)) 65 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_M (BIT(3)) 66 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_V 0x1 67 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL32K_S 3 68 /* MODEM_CLKRST_COEX_LPCLK_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 69 /*description: .*/ 70 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL (BIT(2)) 71 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_M (BIT(2)) 72 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_V 0x1 73 #define MODEM_CLKRST_COEX_LPCLK_SEL_XTAL_S 2 74 /* MODEM_CLKRST_COEX_LPCLK_SEL_8M : R/W ;bitpos:[1] ;default: 1'b0 ; */ 75 /*description: .*/ 76 #define MODEM_CLKRST_COEX_LPCLK_SEL_8M (BIT(1)) 77 #define MODEM_CLKRST_COEX_LPCLK_SEL_8M_M (BIT(1)) 78 #define MODEM_CLKRST_COEX_LPCLK_SEL_8M_V 0x1 79 #define MODEM_CLKRST_COEX_LPCLK_SEL_8M_S 1 80 /* MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ 81 /*description: .*/ 82 #define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW (BIT(0)) 83 #define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_M (BIT(0)) 84 #define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_V 0x1 85 #define MODEM_CLKRST_COEX_LPCLK_SEL_RTC_SLOW_S 0 86 87 #define MODEM_CLKRST_BLE_TIMER_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0xC) 88 /* MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE : R/W ;bitpos:[1] ;default: 1'b1 ; */ 89 /*description: .*/ 90 #define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE (BIT(1)) 91 #define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_M (BIT(1)) 92 #define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_V 0x1 93 #define MODEM_CLKRST_BLETIMER_CLK_IS_ACTIVE_S 1 94 /* MODEM_CLKRST_BLETIMER_USE_XTAL : R/W ;bitpos:[0] ;default: 1'b1 ; */ 95 /*description: .*/ 96 #define MODEM_CLKRST_BLETIMER_USE_XTAL (BIT(0)) 97 #define MODEM_CLKRST_BLETIMER_USE_XTAL_M (BIT(0)) 98 #define MODEM_CLKRST_BLETIMER_USE_XTAL_V 0x1 99 #define MODEM_CLKRST_BLETIMER_USE_XTAL_S 0 100 101 #define MODEM_CLKRST_ETM_CLK_CONF_REG (DR_REG_MODEM_CLKRST_BASE + 0x10) 102 /* MODEM_CLKRST_ETM_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 103 /*description: .*/ 104 #define MODEM_CLKRST_ETM_CLK_ACTIVE (BIT(1)) 105 #define MODEM_CLKRST_ETM_CLK_ACTIVE_M (BIT(1)) 106 #define MODEM_CLKRST_ETM_CLK_ACTIVE_V 0x1 107 #define MODEM_CLKRST_ETM_CLK_ACTIVE_S 1 108 /* MODEM_CLKRST_ETM_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 109 /*description: .*/ 110 #define MODEM_CLKRST_ETM_CLK_SEL (BIT(0)) 111 #define MODEM_CLKRST_ETM_CLK_SEL_M (BIT(0)) 112 #define MODEM_CLKRST_ETM_CLK_SEL_V 0x1 113 #define MODEM_CLKRST_ETM_CLK_SEL_S 0 114 115 #define MODEM_CLKRST_DATE_REG (DR_REG_MODEM_CLKRST_BASE + 0xC) 116 /* MODEM_CLKRST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107270 ; */ 117 /*description: .*/ 118 #define MODEM_CLKRST_DATE 0x0FFFFFFF 119 #define MODEM_CLKRST_DATE_M ((MODEM_CLKRST_DATE_V)<<(MODEM_CLKRST_DATE_S)) 120 #define MODEM_CLKRST_DATE_V 0xFFFFFFF 121 #define MODEM_CLKRST_DATE_S 0 122 123 124 #ifdef __cplusplus 125 } 126 #endif 127
