1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: FIFO Configuration */ 14 /** Type of fifo register 15 * FIFO data register 16 */ 17 typedef union { 18 struct { 19 /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; 20 * UART $n accesses FIFO via this register. 21 */ 22 uint32_t rxfifo_rd_byte:8; 23 uint32_t reserved_8:24; 24 }; 25 uint32_t val; 26 } lp_uart_fifo_reg_t; 27 28 /** Type of mem_conf register 29 * UART memory power configuration 30 */ 31 typedef union { 32 struct { 33 uint32_t reserved_0:25; 34 /** mem_force_pd : R/W; bitpos: [25]; default: 0; 35 * Set this bit to force power down UART memory. 36 */ 37 uint32_t mem_force_pd:1; 38 /** mem_force_pu : R/W; bitpos: [26]; default: 0; 39 * Set this bit to force power up UART memory. 40 */ 41 uint32_t mem_force_pu:1; 42 uint32_t reserved_27:5; 43 }; 44 uint32_t val; 45 } lp_uart_mem_conf_reg_t; 46 47 /** Type of tout_conf_sync register 48 * UART threshold and allocation configuration 49 */ 50 typedef union { 51 struct { 52 /** rx_tout_en : R/W; bitpos: [0]; default: 0; 53 * This is the enble bit for uart receiver's timeout function. 54 */ 55 uint32_t rx_tout_en:1; 56 /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; 57 * Set this bit to stop accumulating idle_cnt when hardware flow control works. 58 */ 59 uint32_t rx_tout_flow_dis:1; 60 /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; 61 * This register is used to configure the threshold time that receiver takes to 62 * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver 63 * takes more time to receive one byte with rx_tout_en set to 1. 64 */ 65 uint32_t rx_tout_thrhd:10; 66 uint32_t reserved_12:20; 67 }; 68 uint32_t val; 69 } lp_uart_tout_conf_sync_reg_t; 70 71 72 /** Group: Interrupt Register */ 73 /** Type of int_raw register 74 * Raw interrupt status 75 */ 76 typedef union { 77 struct { 78 /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 79 * This interrupt raw bit turns to high level when receiver receives more data than 80 * what rxfifo_full_thrhd specifies. 81 */ 82 uint32_t rxfifo_full_int_raw:1; 83 /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; 84 * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is 85 * less than what txfifo_empty_thrhd specifies . 86 */ 87 uint32_t txfifo_empty_int_raw:1; 88 /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 89 * This interrupt raw bit turns to high level when receiver detects a parity error in 90 * the data. 91 */ 92 uint32_t parity_err_int_raw:1; 93 /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 94 * This interrupt raw bit turns to high level when receiver detects a data frame error 95 * . 96 */ 97 uint32_t frm_err_int_raw:1; 98 /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 99 * This interrupt raw bit turns to high level when receiver receives more data than 100 * the FIFO can store. 101 */ 102 uint32_t rxfifo_ovf_int_raw:1; 103 /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 104 * This interrupt raw bit turns to high level when receiver detects the edge change of 105 * DSRn signal. 106 */ 107 uint32_t dsr_chg_int_raw:1; 108 /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 109 * This interrupt raw bit turns to high level when receiver detects the edge change of 110 * CTSn signal. 111 */ 112 uint32_t cts_chg_int_raw:1; 113 /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 114 * This interrupt raw bit turns to high level when receiver detects a 0 after the stop 115 * bit. 116 */ 117 uint32_t brk_det_int_raw:1; 118 /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 119 * This interrupt raw bit turns to high level when receiver takes more time than 120 * rx_tout_thrhd to receive a byte. 121 */ 122 uint32_t rxfifo_tout_int_raw:1; 123 /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 124 * This interrupt raw bit turns to high level when receiver recevies Xon char when 125 * uart_sw_flow_con_en is set to 1. 126 */ 127 uint32_t sw_xon_int_raw:1; 128 /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 129 * This interrupt raw bit turns to high level when receiver receives Xoff char when 130 * uart_sw_flow_con_en is set to 1. 131 */ 132 uint32_t sw_xoff_int_raw:1; 133 /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 134 * This interrupt raw bit turns to high level when receiver detects a glitch in the 135 * middle of a start bit. 136 */ 137 uint32_t glitch_det_int_raw:1; 138 /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 139 * This interrupt raw bit turns to high level when transmitter completes sending 140 * NULL characters after all data in Tx-FIFO are sent. 141 */ 142 uint32_t tx_brk_done_int_raw:1; 143 /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 144 * This interrupt raw bit turns to high level when transmitter has kept the shortest 145 * duration after sending the last data. 146 */ 147 uint32_t tx_brk_idle_done_int_raw:1; 148 /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 149 * This interrupt raw bit turns to high level when transmitter has send out all data 150 * in FIFO. 151 */ 152 uint32_t tx_done_int_raw:1; 153 uint32_t reserved_15:3; 154 /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 155 * This interrupt raw bit turns to high level when receiver detects the configured 156 * at_cmd char. 157 */ 158 uint32_t at_cmd_char_det_int_raw:1; 159 /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 160 * This interrupt raw bit turns to high level when input rxd edge changes more times 161 * than what reg_active_threshold specifies in light sleeping mode. 162 */ 163 uint32_t wakeup_int_raw:1; 164 uint32_t reserved_20:12; 165 }; 166 uint32_t val; 167 } lp_uart_int_raw_reg_t; 168 169 /** Type of int_st register 170 * Masked interrupt status 171 */ 172 typedef union { 173 struct { 174 /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; 175 * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 176 */ 177 uint32_t rxfifo_full_int_st:1; 178 /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; 179 * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set 180 * to 1. 181 */ 182 uint32_t txfifo_empty_int_st:1; 183 /** parity_err_int_st : RO; bitpos: [2]; default: 0; 184 * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 185 */ 186 uint32_t parity_err_int_st:1; 187 /** frm_err_int_st : RO; bitpos: [3]; default: 0; 188 * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 189 */ 190 uint32_t frm_err_int_st:1; 191 /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; 192 * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 193 */ 194 uint32_t rxfifo_ovf_int_st:1; 195 /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; 196 * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 197 */ 198 uint32_t dsr_chg_int_st:1; 199 /** cts_chg_int_st : RO; bitpos: [6]; default: 0; 200 * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 201 */ 202 uint32_t cts_chg_int_st:1; 203 /** brk_det_int_st : RO; bitpos: [7]; default: 0; 204 * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 205 */ 206 uint32_t brk_det_int_st:1; 207 /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; 208 * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 209 */ 210 uint32_t rxfifo_tout_int_st:1; 211 /** sw_xon_int_st : RO; bitpos: [9]; default: 0; 212 * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 213 */ 214 uint32_t sw_xon_int_st:1; 215 /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; 216 * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 217 */ 218 uint32_t sw_xoff_int_st:1; 219 /** glitch_det_int_st : RO; bitpos: [11]; default: 0; 220 * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 221 */ 222 uint32_t glitch_det_int_st:1; 223 /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; 224 * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 225 */ 226 uint32_t tx_brk_done_int_st:1; 227 /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; 228 * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena 229 * is set to 1. 230 */ 231 uint32_t tx_brk_idle_done_int_st:1; 232 /** tx_done_int_st : RO; bitpos: [14]; default: 0; 233 * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 234 */ 235 uint32_t tx_done_int_st:1; 236 uint32_t reserved_15:3; 237 /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; 238 * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set 239 * to 1. 240 */ 241 uint32_t at_cmd_char_det_int_st:1; 242 /** wakeup_int_st : RO; bitpos: [19]; default: 0; 243 * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 244 */ 245 uint32_t wakeup_int_st:1; 246 uint32_t reserved_20:12; 247 }; 248 uint32_t val; 249 } lp_uart_int_st_reg_t; 250 251 /** Type of int_ena register 252 * Interrupt enable bits 253 */ 254 typedef union { 255 struct { 256 /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; 257 * This is the enable bit for rxfifo_full_int_st register. 258 */ 259 uint32_t rxfifo_full_int_ena:1; 260 /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; 261 * This is the enable bit for txfifo_empty_int_st register. 262 */ 263 uint32_t txfifo_empty_int_ena:1; 264 /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; 265 * This is the enable bit for parity_err_int_st register. 266 */ 267 uint32_t parity_err_int_ena:1; 268 /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; 269 * This is the enable bit for frm_err_int_st register. 270 */ 271 uint32_t frm_err_int_ena:1; 272 /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; 273 * This is the enable bit for rxfifo_ovf_int_st register. 274 */ 275 uint32_t rxfifo_ovf_int_ena:1; 276 /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; 277 * This is the enable bit for dsr_chg_int_st register. 278 */ 279 uint32_t dsr_chg_int_ena:1; 280 /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; 281 * This is the enable bit for cts_chg_int_st register. 282 */ 283 uint32_t cts_chg_int_ena:1; 284 /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; 285 * This is the enable bit for brk_det_int_st register. 286 */ 287 uint32_t brk_det_int_ena:1; 288 /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; 289 * This is the enable bit for rxfifo_tout_int_st register. 290 */ 291 uint32_t rxfifo_tout_int_ena:1; 292 /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; 293 * This is the enable bit for sw_xon_int_st register. 294 */ 295 uint32_t sw_xon_int_ena:1; 296 /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; 297 * This is the enable bit for sw_xoff_int_st register. 298 */ 299 uint32_t sw_xoff_int_ena:1; 300 /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; 301 * This is the enable bit for glitch_det_int_st register. 302 */ 303 uint32_t glitch_det_int_ena:1; 304 /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; 305 * This is the enable bit for tx_brk_done_int_st register. 306 */ 307 uint32_t tx_brk_done_int_ena:1; 308 /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; 309 * This is the enable bit for tx_brk_idle_done_int_st register. 310 */ 311 uint32_t tx_brk_idle_done_int_ena:1; 312 /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; 313 * This is the enable bit for tx_done_int_st register. 314 */ 315 uint32_t tx_done_int_ena:1; 316 uint32_t reserved_15:3; 317 /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; 318 * This is the enable bit for at_cmd_char_det_int_st register. 319 */ 320 uint32_t at_cmd_char_det_int_ena:1; 321 /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; 322 * This is the enable bit for uart_wakeup_int_st register. 323 */ 324 uint32_t wakeup_int_ena:1; 325 uint32_t reserved_20:12; 326 }; 327 uint32_t val; 328 } lp_uart_int_ena_reg_t; 329 330 /** Type of int_clr register 331 * Interrupt clear bits 332 */ 333 typedef union { 334 struct { 335 /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; 336 * Set this bit to clear the rxfifo_full_int_raw interrupt. 337 */ 338 uint32_t rxfifo_full_int_clr:1; 339 /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; 340 * Set this bit to clear txfifo_empty_int_raw interrupt. 341 */ 342 uint32_t txfifo_empty_int_clr:1; 343 /** parity_err_int_clr : WT; bitpos: [2]; default: 0; 344 * Set this bit to clear parity_err_int_raw interrupt. 345 */ 346 uint32_t parity_err_int_clr:1; 347 /** frm_err_int_clr : WT; bitpos: [3]; default: 0; 348 * Set this bit to clear frm_err_int_raw interrupt. 349 */ 350 uint32_t frm_err_int_clr:1; 351 /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; 352 * Set this bit to clear rxfifo_ovf_int_raw interrupt. 353 */ 354 uint32_t rxfifo_ovf_int_clr:1; 355 /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; 356 * Set this bit to clear the dsr_chg_int_raw interrupt. 357 */ 358 uint32_t dsr_chg_int_clr:1; 359 /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; 360 * Set this bit to clear the cts_chg_int_raw interrupt. 361 */ 362 uint32_t cts_chg_int_clr:1; 363 /** brk_det_int_clr : WT; bitpos: [7]; default: 0; 364 * Set this bit to clear the brk_det_int_raw interrupt. 365 */ 366 uint32_t brk_det_int_clr:1; 367 /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; 368 * Set this bit to clear the rxfifo_tout_int_raw interrupt. 369 */ 370 uint32_t rxfifo_tout_int_clr:1; 371 /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; 372 * Set this bit to clear the sw_xon_int_raw interrupt. 373 */ 374 uint32_t sw_xon_int_clr:1; 375 /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; 376 * Set this bit to clear the sw_xoff_int_raw interrupt. 377 */ 378 uint32_t sw_xoff_int_clr:1; 379 /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; 380 * Set this bit to clear the glitch_det_int_raw interrupt. 381 */ 382 uint32_t glitch_det_int_clr:1; 383 /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; 384 * Set this bit to clear the tx_brk_done_int_raw interrupt.. 385 */ 386 uint32_t tx_brk_done_int_clr:1; 387 /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; 388 * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 389 */ 390 uint32_t tx_brk_idle_done_int_clr:1; 391 /** tx_done_int_clr : WT; bitpos: [14]; default: 0; 392 * Set this bit to clear the tx_done_int_raw interrupt. 393 */ 394 uint32_t tx_done_int_clr:1; 395 uint32_t reserved_15:3; 396 /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; 397 * Set this bit to clear the at_cmd_char_det_int_raw interrupt. 398 */ 399 uint32_t at_cmd_char_det_int_clr:1; 400 /** wakeup_int_clr : WT; bitpos: [19]; default: 0; 401 * Set this bit to clear the uart_wakeup_int_raw interrupt. 402 */ 403 uint32_t wakeup_int_clr:1; 404 uint32_t reserved_20:12; 405 }; 406 uint32_t val; 407 } lp_uart_int_clr_reg_t; 408 409 410 /** Group: Configuration Register */ 411 /** Type of clkdiv_sync register 412 * Clock divider configuration 413 */ 414 typedef union { 415 struct { 416 /** clkdiv : R/W; bitpos: [11:0]; default: 694; 417 * The integral part of the frequency divider factor. 418 */ 419 uint32_t clkdiv:12; 420 uint32_t reserved_12:8; 421 /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; 422 * The decimal part of the frequency divider factor. 423 */ 424 uint32_t clkdiv_frag:4; 425 uint32_t reserved_24:8; 426 }; 427 uint32_t val; 428 } lp_uart_clkdiv_sync_reg_t; 429 430 /** Type of rx_filt register 431 * Rx Filter configuration 432 */ 433 typedef union { 434 struct { 435 /** glitch_filt : R/W; bitpos: [7:0]; default: 8; 436 * when input pulse width is lower than this value the pulse is ignored. 437 */ 438 uint32_t glitch_filt:8; 439 /** glitch_filt_en : R/W; bitpos: [8]; default: 0; 440 * Set this bit to enable Rx signal filter. 441 */ 442 uint32_t glitch_filt_en:1; 443 uint32_t reserved_9:23; 444 }; 445 uint32_t val; 446 } lp_uart_rx_filt_reg_t; 447 448 /** Type of conf0_sync register 449 * Configuration register 0 450 */ 451 typedef union { 452 struct { 453 /** parity : R/W; bitpos: [0]; default: 0; 454 * This register is used to configure the parity check mode. 455 */ 456 uint32_t parity:1; 457 /** parity_en : R/W; bitpos: [1]; default: 0; 458 * Set this bit to enable uart parity check. 459 */ 460 uint32_t parity_en:1; 461 /** bit_num : R/W; bitpos: [3:2]; default: 3; 462 * This register is used to set the length of data. 463 */ 464 uint32_t bit_num:2; 465 /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; 466 * This register is used to set the length of stop bit. 467 */ 468 uint32_t stop_bit_num:2; 469 /** txd_brk : R/W; bitpos: [6]; default: 0; 470 * Set this bit to enbale transmitter to send NULL when the process of sending data 471 * is done. 472 */ 473 uint32_t txd_brk:1; 474 uint32_t reserved_7:5; 475 /** loopback : R/W; bitpos: [12]; default: 0; 476 * Set this bit to enable uart loopback test mode. 477 */ 478 uint32_t loopback:1; 479 /** tx_flow_en : R/W; bitpos: [13]; default: 0; 480 * Set this bit to enable flow control function for transmitter. 481 */ 482 uint32_t tx_flow_en:1; 483 uint32_t reserved_14:1; 484 /** rxd_inv : R/W; bitpos: [15]; default: 0; 485 * Set this bit to inverse the level value of uart rxd signal. 486 */ 487 uint32_t rxd_inv:1; 488 /** txd_inv : R/W; bitpos: [16]; default: 0; 489 * Set this bit to inverse the level value of uart txd signal. 490 */ 491 uint32_t txd_inv:1; 492 /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; 493 * Disable UART Rx data overflow detect. 494 */ 495 uint32_t dis_rx_dat_ovf:1; 496 /** err_wr_mask : R/W; bitpos: [18]; default: 0; 497 * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver 498 * stores the data even if the received data is wrong. 499 */ 500 uint32_t err_wr_mask:1; 501 uint32_t reserved_19:1; 502 /** mem_clk_en : R/W; bitpos: [20]; default: 0; 503 * UART memory clock gate enable signal. 504 */ 505 uint32_t mem_clk_en:1; 506 /** sw_rts : R/W; bitpos: [21]; default: 0; 507 * This register is used to configure the software rts signal which is used in 508 * software flow control. 509 */ 510 uint32_t sw_rts:1; 511 /** rxfifo_rst : R/W; bitpos: [22]; default: 0; 512 * Set this bit to reset the uart receive-FIFO. 513 */ 514 uint32_t rxfifo_rst:1; 515 /** txfifo_rst : R/W; bitpos: [23]; default: 0; 516 * Set this bit to reset the uart transmit-FIFO. 517 */ 518 uint32_t txfifo_rst:1; 519 uint32_t reserved_24:8; 520 }; 521 uint32_t val; 522 } lp_uart_conf0_sync_reg_t; 523 524 /** Type of conf1 register 525 * Configuration register 1 526 */ 527 typedef union { 528 struct { 529 uint32_t reserved_0:3; 530 /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12; 531 * It will produce rxfifo_full_int interrupt when receiver receives more data than 532 * this register value. 533 */ 534 uint32_t rxfifo_full_thrhd:5; 535 uint32_t reserved_8:3; 536 /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12; 537 * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less 538 * than this register value. 539 */ 540 uint32_t txfifo_empty_thrhd:5; 541 /** cts_inv : R/W; bitpos: [16]; default: 0; 542 * Set this bit to inverse the level value of uart cts signal. 543 */ 544 uint32_t cts_inv:1; 545 /** dsr_inv : R/W; bitpos: [17]; default: 0; 546 * Set this bit to inverse the level value of uart dsr signal. 547 */ 548 uint32_t dsr_inv:1; 549 /** rts_inv : R/W; bitpos: [18]; default: 0; 550 * Set this bit to inverse the level value of uart rts signal. 551 */ 552 uint32_t rts_inv:1; 553 /** dtr_inv : R/W; bitpos: [19]; default: 0; 554 * Set this bit to inverse the level value of uart dtr signal. 555 */ 556 uint32_t dtr_inv:1; 557 /** sw_dtr : R/W; bitpos: [20]; default: 0; 558 * This register is used to configure the software dtr signal which is used in 559 * software flow control. 560 */ 561 uint32_t sw_dtr:1; 562 /** clk_en : R/W; bitpos: [21]; default: 0; 563 * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes 564 * registers. 565 */ 566 uint32_t clk_en:1; 567 uint32_t reserved_22:10; 568 }; 569 uint32_t val; 570 } lp_uart_conf1_reg_t; 571 572 /** Type of hwfc_conf_sync register 573 * Hardware flow-control configuration 574 */ 575 typedef union { 576 struct { 577 uint32_t reserved_0:3; 578 /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0; 579 * This register is used to configure the maximum amount of data that can be received 580 * when hardware flow control works. 581 */ 582 uint32_t rx_flow_thrhd:5; 583 /** rx_flow_en : R/W; bitpos: [8]; default: 0; 584 * This is the flow enable bit for UART receiver. 585 */ 586 uint32_t rx_flow_en:1; 587 uint32_t reserved_9:23; 588 }; 589 uint32_t val; 590 } lp_uart_hwfc_conf_sync_reg_t; 591 592 /** Type of sleep_conf0 register 593 * UART sleep configure register 0 594 */ 595 typedef union { 596 struct { 597 /** wk_char1 : R/W; bitpos: [7:0]; default: 0; 598 * This register restores the specified wake up char1 to wake up 599 */ 600 uint32_t wk_char1:8; 601 /** wk_char2 : R/W; bitpos: [15:8]; default: 0; 602 * This register restores the specified wake up char2 to wake up 603 */ 604 uint32_t wk_char2:8; 605 /** wk_char3 : R/W; bitpos: [23:16]; default: 0; 606 * This register restores the specified wake up char3 to wake up 607 */ 608 uint32_t wk_char3:8; 609 /** wk_char4 : R/W; bitpos: [31:24]; default: 0; 610 * This register restores the specified wake up char4 to wake up 611 */ 612 uint32_t wk_char4:8; 613 }; 614 uint32_t val; 615 } lp_uart_sleep_conf0_reg_t; 616 617 /** Type of sleep_conf1 register 618 * UART sleep configure register 1 619 */ 620 typedef union { 621 struct { 622 /** wk_char0 : R/W; bitpos: [7:0]; default: 0; 623 * This register restores the specified char0 to wake up 624 */ 625 uint32_t wk_char0:8; 626 uint32_t reserved_8:24; 627 }; 628 uint32_t val; 629 } lp_uart_sleep_conf1_reg_t; 630 631 /** Type of sleep_conf2 register 632 * UART sleep configure register 2 633 */ 634 typedef union { 635 struct { 636 /** active_threshold : R/W; bitpos: [9:0]; default: 240; 637 * The uart is activated from light sleeping mode when the input rxd edge changes more 638 * times than this register value. 639 */ 640 uint32_t active_threshold:10; 641 uint32_t reserved_10:3; 642 /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1; 643 * In wake up mode 1 this field is used to set the received data number threshold to 644 * wake up chip. 645 */ 646 uint32_t rx_wake_up_thrhd:5; 647 /** wk_char_num : R/W; bitpos: [20:18]; default: 5; 648 * This register is used to select number of wake up char. 649 */ 650 uint32_t wk_char_num:3; 651 /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; 652 * This register is used to mask wake up char. 653 */ 654 uint32_t wk_char_mask:5; 655 /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; 656 * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: 657 * received data number larger than 658 */ 659 uint32_t wk_mode_sel:2; 660 uint32_t reserved_28:4; 661 }; 662 uint32_t val; 663 } lp_uart_sleep_conf2_reg_t; 664 665 /** Type of swfc_conf0_sync register 666 * Software flow-control character configuration 667 */ 668 typedef union { 669 struct { 670 /** xon_char : R/W; bitpos: [7:0]; default: 17; 671 * This register stores the Xon flow control char. 672 */ 673 uint32_t xon_char:8; 674 /** xoff_char : R/W; bitpos: [15:8]; default: 19; 675 * This register stores the Xoff flow control char. 676 */ 677 uint32_t xoff_char:8; 678 /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; 679 * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In 680 * this status, UART Tx can not transmit XOFF even the received data number is larger 681 * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when 682 * UART Tx is disabled. 683 */ 684 uint32_t xon_xoff_still_send:1; 685 /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; 686 * Set this bit to enable software flow control. It is used with register sw_xon or 687 * sw_xoff. 688 */ 689 uint32_t sw_flow_con_en:1; 690 /** xonoff_del : R/W; bitpos: [18]; default: 0; 691 * Set this bit to remove flow control char from the received data. 692 */ 693 uint32_t xonoff_del:1; 694 /** force_xon : R/W; bitpos: [19]; default: 0; 695 * Set this bit to enable the transmitter to go on sending data. 696 */ 697 uint32_t force_xon:1; 698 /** force_xoff : R/W; bitpos: [20]; default: 0; 699 * Set this bit to stop the transmitter from sending data. 700 */ 701 uint32_t force_xoff:1; 702 /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; 703 * Set this bit to send Xon char. It is cleared by hardware automatically. 704 */ 705 uint32_t send_xon:1; 706 /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; 707 * Set this bit to send Xoff char. It is cleared by hardware automatically. 708 */ 709 uint32_t send_xoff:1; 710 uint32_t reserved_23:9; 711 }; 712 uint32_t val; 713 } lp_uart_swfc_conf0_sync_reg_t; 714 715 /** Type of swfc_conf1 register 716 * Software flow-control character configuration 717 */ 718 typedef union { 719 struct { 720 uint32_t reserved_0:3; 721 /** xon_threshold : R/W; bitpos: [7:3]; default: 0; 722 * When the data amount in Rx-FIFO is less than this register value with 723 * uart_sw_flow_con_en set to 1 it will send a Xon char. 724 */ 725 uint32_t xon_threshold:5; 726 uint32_t reserved_8:3; 727 /** xoff_threshold : R/W; bitpos: [15:11]; default: 12; 728 * When the data amount in Rx-FIFO is more than this register value with 729 * uart_sw_flow_con_en set to 1 it will send a Xoff char. 730 */ 731 uint32_t xoff_threshold:5; 732 uint32_t reserved_16:16; 733 }; 734 uint32_t val; 735 } lp_uart_swfc_conf1_reg_t; 736 737 /** Type of txbrk_conf_sync register 738 * Tx Break character configuration 739 */ 740 typedef union { 741 struct { 742 /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; 743 * This register is used to configure the number of 0 to be sent after the process of 744 * sending data is done. It is active when txd_brk is set to 1. 745 */ 746 uint32_t tx_brk_num:8; 747 uint32_t reserved_8:24; 748 }; 749 uint32_t val; 750 } lp_uart_txbrk_conf_sync_reg_t; 751 752 /** Type of idle_conf_sync register 753 * Frame-end idle configuration 754 */ 755 typedef union { 756 struct { 757 /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; 758 * It will produce frame end signal when receiver takes more time to receive one byte 759 * data than this register value. 760 */ 761 uint32_t rx_idle_thrhd:10; 762 /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; 763 * This register is used to configure the duration time between transfers. 764 */ 765 uint32_t tx_idle_num:10; 766 uint32_t reserved_20:12; 767 }; 768 uint32_t val; 769 } lp_uart_idle_conf_sync_reg_t; 770 771 /** Type of rs485_conf_sync register 772 * RS485 mode configuration 773 */ 774 typedef union { 775 struct { 776 uint32_t reserved_0:1; 777 /** dl0_en : R/W; bitpos: [1]; default: 0; 778 * Set this bit to delay the stop bit by 1 bit. 779 */ 780 uint32_t dl0_en:1; 781 /** dl1_en : R/W; bitpos: [2]; default: 0; 782 * Set this bit to delay the stop bit by 1 bit. 783 */ 784 uint32_t dl1_en:1; 785 uint32_t reserved_3:29; 786 }; 787 uint32_t val; 788 } lp_uart_rs485_conf_sync_reg_t; 789 790 /** Type of clk_conf register 791 * UART core clock configuration 792 */ 793 typedef union { 794 struct { 795 uint32_t reserved_0:24; 796 /** tx_sclk_en : R/W; bitpos: [24]; default: 1; 797 * Set this bit to enable UART Tx clock. 798 */ 799 uint32_t tx_sclk_en:1; 800 /** rx_sclk_en : R/W; bitpos: [25]; default: 1; 801 * Set this bit to enable UART Rx clock. 802 */ 803 uint32_t rx_sclk_en:1; 804 /** tx_rst_core : R/W; bitpos: [26]; default: 0; 805 * Write 1 then write 0 to this bit to reset UART Tx. 806 */ 807 uint32_t tx_rst_core:1; 808 /** rx_rst_core : R/W; bitpos: [27]; default: 0; 809 * Write 1 then write 0 to this bit to reset UART Rx. 810 */ 811 uint32_t rx_rst_core:1; 812 uint32_t reserved_28:4; 813 }; 814 uint32_t val; 815 } lp_uart_clk_conf_reg_t; 816 817 818 /** Group: Status Register */ 819 /** Type of status register 820 * UART status register 821 */ 822 typedef union { 823 struct { 824 uint32_t reserved_0:3; 825 /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0; 826 * Stores the byte number of valid data in Rx-FIFO. 827 */ 828 uint32_t rxfifo_cnt:5; 829 uint32_t reserved_8:5; 830 /** dsrn : RO; bitpos: [13]; default: 0; 831 * The register represent the level value of the internal uart dsr signal. 832 */ 833 uint32_t dsrn:1; 834 /** ctsn : RO; bitpos: [14]; default: 1; 835 * This register represent the level value of the internal uart cts signal. 836 */ 837 uint32_t ctsn:1; 838 /** rxd : RO; bitpos: [15]; default: 1; 839 * This register represent the level value of the internal uart rxd signal. 840 */ 841 uint32_t rxd:1; 842 uint32_t reserved_16:3; 843 /** txfifo_cnt : RO; bitpos: [23:19]; default: 0; 844 * Stores the byte number of data in Tx-FIFO. 845 */ 846 uint32_t txfifo_cnt:5; 847 uint32_t reserved_24:5; 848 /** dtrn : RO; bitpos: [29]; default: 1; 849 * This bit represents the level of the internal uart dtr signal. 850 */ 851 uint32_t dtrn:1; 852 /** rtsn : RO; bitpos: [30]; default: 1; 853 * This bit represents the level of the internal uart rts signal. 854 */ 855 uint32_t rtsn:1; 856 /** txd : RO; bitpos: [31]; default: 1; 857 * This bit represents the level of the internal uart txd signal. 858 */ 859 uint32_t txd:1; 860 }; 861 uint32_t val; 862 } lp_uart_status_reg_t; 863 864 /** Type of mem_tx_status register 865 * Tx-SRAM write and read offset address. 866 */ 867 typedef union { 868 struct { 869 uint32_t reserved_0:3; 870 /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0; 871 * This register stores the offset write address in Tx-SRAM. 872 */ 873 uint32_t tx_sram_waddr:5; 874 uint32_t reserved_8:4; 875 /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0; 876 * This register stores the offset read address in Tx-SRAM. 877 */ 878 uint32_t tx_sram_raddr:5; 879 uint32_t reserved_17:15; 880 }; 881 uint32_t val; 882 } lp_uart_mem_tx_status_reg_t; 883 884 /** Type of mem_rx_status register 885 * Rx-SRAM write and read offset address. 886 */ 887 typedef union { 888 struct { 889 uint32_t reserved_0:3; 890 /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16; 891 * This register stores the offset read address in RX-SRAM. 892 */ 893 uint32_t rx_sram_raddr:5; 894 uint32_t reserved_8:4; 895 /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16; 896 * This register stores the offset write address in Rx-SRAM. 897 */ 898 uint32_t rx_sram_waddr:5; 899 uint32_t reserved_17:15; 900 }; 901 uint32_t val; 902 } lp_uart_mem_rx_status_reg_t; 903 904 /** Type of fsm_status register 905 * UART transmit and receive status. 906 */ 907 typedef union { 908 struct { 909 /** st_urx_out : RO; bitpos: [3:0]; default: 0; 910 * This is the status register of receiver. 911 */ 912 uint32_t st_urx_out:4; 913 /** st_utx_out : RO; bitpos: [7:4]; default: 0; 914 * This is the status register of transmitter. 915 */ 916 uint32_t st_utx_out:4; 917 uint32_t reserved_8:24; 918 }; 919 uint32_t val; 920 } lp_uart_fsm_status_reg_t; 921 922 /** Type of afifo_status register 923 * UART AFIFO Status 924 */ 925 typedef union { 926 struct { 927 /** tx_afifo_full : RO; bitpos: [0]; default: 0; 928 * Full signal of APB TX AFIFO. 929 */ 930 uint32_t tx_afifo_full:1; 931 /** tx_afifo_empty : RO; bitpos: [1]; default: 1; 932 * Empty signal of APB TX AFIFO. 933 */ 934 uint32_t tx_afifo_empty:1; 935 /** rx_afifo_full : RO; bitpos: [2]; default: 0; 936 * Full signal of APB RX AFIFO. 937 */ 938 uint32_t rx_afifo_full:1; 939 /** rx_afifo_empty : RO; bitpos: [3]; default: 1; 940 * Empty signal of APB RX AFIFO. 941 */ 942 uint32_t rx_afifo_empty:1; 943 uint32_t reserved_4:28; 944 }; 945 uint32_t val; 946 } lp_uart_afifo_status_reg_t; 947 948 949 /** Group: AT Escape Sequence Selection Configuration */ 950 /** Type of at_cmd_precnt_sync register 951 * Pre-sequence timing configuration 952 */ 953 typedef union { 954 struct { 955 /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; 956 * This register is used to configure the idle duration time before the first at_cmd 957 * is received by receiver. 958 */ 959 uint32_t pre_idle_num:16; 960 uint32_t reserved_16:16; 961 }; 962 uint32_t val; 963 } lp_uart_at_cmd_precnt_sync_reg_t; 964 965 /** Type of at_cmd_postcnt_sync register 966 * Post-sequence timing configuration 967 */ 968 typedef union { 969 struct { 970 /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; 971 * This register is used to configure the duration time between the last at_cmd and 972 * the next data. 973 */ 974 uint32_t post_idle_num:16; 975 uint32_t reserved_16:16; 976 }; 977 uint32_t val; 978 } lp_uart_at_cmd_postcnt_sync_reg_t; 979 980 /** Type of at_cmd_gaptout_sync register 981 * Timeout configuration 982 */ 983 typedef union { 984 struct { 985 /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; 986 * This register is used to configure the duration time between the at_cmd chars. 987 */ 988 uint32_t rx_gap_tout:16; 989 uint32_t reserved_16:16; 990 }; 991 uint32_t val; 992 } lp_uart_at_cmd_gaptout_sync_reg_t; 993 994 /** Type of at_cmd_char_sync register 995 * AT escape sequence detection configuration 996 */ 997 typedef union { 998 struct { 999 /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; 1000 * This register is used to configure the content of at_cmd char. 1001 */ 1002 uint32_t at_cmd_char:8; 1003 /** char_num : R/W; bitpos: [15:8]; default: 3; 1004 * This register is used to configure the num of continuous at_cmd chars received by 1005 * receiver. 1006 */ 1007 uint32_t char_num:8; 1008 uint32_t reserved_16:16; 1009 }; 1010 uint32_t val; 1011 } lp_uart_at_cmd_char_sync_reg_t; 1012 1013 1014 /** Group: Version Register */ 1015 /** Type of date register 1016 * UART Version register 1017 */ 1018 typedef union { 1019 struct { 1020 /** date : R/W; bitpos: [31:0]; default: 36720720; 1021 * This is the version register. 1022 */ 1023 uint32_t date:32; 1024 }; 1025 uint32_t val; 1026 } lp_uart_date_reg_t; 1027 1028 /** Type of reg_update register 1029 * UART Registers Configuration Update register 1030 */ 1031 typedef union { 1032 struct { 1033 /** reg_update : R/W/SC; bitpos: [0]; default: 0; 1034 * Software write 1 would synchronize registers into UART Core clock domain and would 1035 * be cleared by hardware after synchronization is done. 1036 */ 1037 uint32_t reg_update:1; 1038 uint32_t reserved_1:31; 1039 }; 1040 uint32_t val; 1041 } lp_uart_reg_update_reg_t; 1042 1043 /** Type of id register 1044 * UART ID register 1045 */ 1046 typedef union { 1047 struct { 1048 /** id : R/W; bitpos: [31:0]; default: 1280; 1049 * This register is used to configure the uart_id. 1050 */ 1051 uint32_t id:32; 1052 }; 1053 uint32_t val; 1054 } lp_uart_id_reg_t; 1055 1056 1057 typedef struct { 1058 volatile lp_uart_fifo_reg_t fifo; 1059 volatile lp_uart_int_raw_reg_t int_raw; 1060 volatile lp_uart_int_st_reg_t int_st; 1061 volatile lp_uart_int_ena_reg_t int_ena; 1062 volatile lp_uart_int_clr_reg_t int_clr; 1063 volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync; 1064 volatile lp_uart_rx_filt_reg_t rx_filt; 1065 volatile lp_uart_status_reg_t status; 1066 volatile lp_uart_conf0_sync_reg_t conf0_sync; 1067 volatile lp_uart_conf1_reg_t conf1; 1068 uint32_t reserved_028; 1069 volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync; 1070 volatile lp_uart_sleep_conf0_reg_t sleep_conf0; 1071 volatile lp_uart_sleep_conf1_reg_t sleep_conf1; 1072 volatile lp_uart_sleep_conf2_reg_t sleep_conf2; 1073 volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync; 1074 volatile lp_uart_swfc_conf1_reg_t swfc_conf1; 1075 volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync; 1076 volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync; 1077 volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync; 1078 volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; 1079 volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; 1080 volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; 1081 volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync; 1082 volatile lp_uart_mem_conf_reg_t mem_conf; 1083 volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync; 1084 volatile lp_uart_mem_tx_status_reg_t mem_tx_status; 1085 volatile lp_uart_mem_rx_status_reg_t mem_rx_status; 1086 volatile lp_uart_fsm_status_reg_t fsm_status; 1087 uint32_t reserved_074[5]; 1088 volatile lp_uart_clk_conf_reg_t clk_conf; 1089 volatile lp_uart_date_reg_t date; 1090 volatile lp_uart_afifo_status_reg_t afifo_status; 1091 uint32_t reserved_094; 1092 volatile lp_uart_reg_update_reg_t reg_update; 1093 volatile lp_uart_id_reg_t id; 1094 } lp_uart_dev_t; 1095 1096 1097 #ifndef __cplusplus 1098 _Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); 1099 #endif 1100 1101 #ifdef __cplusplus 1102 } 1103 #endif 1104
