1 /** 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Timing registers */ 14 /** Type of scl_low_period register 15 * Configures the low level width of the SCL 16 * Clock 17 */ 18 typedef union { 19 struct { 20 /** scl_low_period : R/W; bitpos: [8:0]; default: 0; 21 * This register is used to configure for how long SCL remains low in master mode, in 22 * I2C module clock cycles. 23 */ 24 uint32_t scl_low_period:9; 25 uint32_t reserved_9:23; 26 }; 27 uint32_t val; 28 } lp_i2c_scl_low_period_reg_t; 29 30 /** Type of sda_hold register 31 * Configures the hold time after a negative SCL edge. 32 */ 33 typedef union { 34 struct { 35 /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; 36 * This register is used to configure the time to hold the data after the negative 37 * edge of SCL, in I2C module clock cycles. 38 */ 39 uint32_t sda_hold_time:9; 40 uint32_t reserved_9:23; 41 }; 42 uint32_t val; 43 } lp_i2c_sda_hold_reg_t; 44 45 /** Type of sda_sample register 46 * Configures the sample time after a positive SCL edge. 47 */ 48 typedef union { 49 struct { 50 /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; 51 * This register is used to configure for how long SDA is sampled, in I2C module clock 52 * cycles. 53 */ 54 uint32_t sda_sample_time:9; 55 uint32_t reserved_9:23; 56 }; 57 uint32_t val; 58 } lp_i2c_sda_sample_reg_t; 59 60 /** Type of scl_high_period register 61 * Configures the high level width of SCL 62 */ 63 typedef union { 64 struct { 65 /** scl_high_period : R/W; bitpos: [8:0]; default: 0; 66 * This register is used to configure for how long SCL setup to high level and remains 67 * high in master mode, in I2C module clock cycles. 68 */ 69 uint32_t scl_high_period:9; 70 /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; 71 * This register is used to configure for the SCL_FSM's waiting period for SCL high 72 * level in master mode, in I2C module clock cycles. 73 */ 74 uint32_t scl_wait_high_period:7; 75 uint32_t reserved_16:16; 76 }; 77 uint32_t val; 78 } lp_i2c_scl_high_period_reg_t; 79 80 /** Type of scl_start_hold register 81 * Configures the delay between the SDA and SCL negative edge for a start condition 82 */ 83 typedef union { 84 struct { 85 /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; 86 * This register is used to configure the time between the negative edge 87 * of SDA and the negative edge of SCL for a START condition, in I2C module clock 88 * cycles. 89 */ 90 uint32_t scl_start_hold_time:9; 91 uint32_t reserved_9:23; 92 }; 93 uint32_t val; 94 } lp_i2c_scl_start_hold_reg_t; 95 96 /** Type of scl_rstart_setup register 97 * Configures the delay between the positive 98 * edge of SCL and the negative edge of SDA 99 */ 100 typedef union { 101 struct { 102 /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; 103 * This register is used to configure the time between the positive 104 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module 105 * clock cycles. 106 */ 107 uint32_t scl_rstart_setup_time:9; 108 uint32_t reserved_9:23; 109 }; 110 uint32_t val; 111 } lp_i2c_scl_rstart_setup_reg_t; 112 113 /** Type of scl_stop_hold register 114 * Configures the delay after the SCL clock 115 * edge for a stop condition 116 */ 117 typedef union { 118 struct { 119 /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; 120 * This register is used to configure the delay after the STOP condition, 121 * in I2C module clock cycles. 122 */ 123 uint32_t scl_stop_hold_time:9; 124 uint32_t reserved_9:23; 125 }; 126 uint32_t val; 127 } lp_i2c_scl_stop_hold_reg_t; 128 129 /** Type of scl_stop_setup register 130 * Configures the delay between the SDA and 131 * SCL positive edge for a stop condition 132 */ 133 typedef union { 134 struct { 135 /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; 136 * This register is used to configure the time between the positive edge 137 * of SCL and the positive edge of SDA, in I2C module clock cycles. 138 */ 139 uint32_t scl_stop_setup_time:9; 140 uint32_t reserved_9:23; 141 }; 142 uint32_t val; 143 } lp_i2c_scl_stop_setup_reg_t; 144 145 /** Type of scl_st_time_out register 146 * SCL status time out register 147 */ 148 typedef union { 149 struct { 150 /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; 151 * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 152 */ 153 uint32_t scl_st_to_i2c:5; 154 uint32_t reserved_5:27; 155 }; 156 uint32_t val; 157 } lp_i2c_scl_st_time_out_reg_t; 158 159 /** Type of scl_main_st_time_out register 160 * SCL main status time out register 161 */ 162 typedef union { 163 struct { 164 /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; 165 * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more 166 * than 23 167 */ 168 uint32_t scl_main_st_to_i2c:5; 169 uint32_t reserved_5:27; 170 }; 171 uint32_t val; 172 } lp_i2c_scl_main_st_time_out_reg_t; 173 174 175 /** Group: Configuration registers */ 176 /** Type of ctr register 177 * Transmission setting 178 */ 179 typedef union { 180 struct { 181 /** sda_force_out : R/W; bitpos: [0]; default: 0; 182 * 1: direct output, 0: open drain output. 183 */ 184 uint32_t sda_force_out:1; 185 /** scl_force_out : R/W; bitpos: [1]; default: 0; 186 * 1: direct output, 0: open drain output. 187 */ 188 uint32_t scl_force_out:1; 189 /** sample_scl_level : R/W; bitpos: [2]; default: 0; 190 * This register is used to select the sample mode. 191 * 1: sample SDA data on the SCL low level. 192 * 0: sample SDA data on the SCL high level. 193 */ 194 uint32_t sample_scl_level:1; 195 /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; 196 * This register is used to configure the ACK value that need to sent by master when 197 * the rx_fifo_cnt has reached the threshold. 198 */ 199 uint32_t rx_full_ack_level:1; 200 uint32_t reserved_4:1; 201 /** trans_start : WT; bitpos: [5]; default: 0; 202 * Set this bit to start sending the data in txfifo. 203 */ 204 uint32_t trans_start:1; 205 /** tx_lsb_first : R/W; bitpos: [6]; default: 0; 206 * This bit is used to control the sending mode for data needing to be sent. 207 * 1: send data from the least significant bit, 208 * 0: send data from the most significant bit. 209 */ 210 uint32_t tx_lsb_first:1; 211 /** rx_lsb_first : R/W; bitpos: [7]; default: 0; 212 * This bit is used to control the storage mode for received data. 213 * 1: receive data from the least significant bit, 214 * 0: receive data from the most significant bit. 215 */ 216 uint32_t rx_lsb_first:1; 217 /** clk_en : R/W; bitpos: [8]; default: 0; 218 * Reserved 219 */ 220 uint32_t clk_en:1; 221 /** arbitration_en : R/W; bitpos: [9]; default: 1; 222 * This is the enable bit for arbitration_lost. 223 */ 224 uint32_t arbitration_en:1; 225 /** fsm_rst : WT; bitpos: [10]; default: 0; 226 * This register is used to reset the scl FMS. 227 */ 228 uint32_t fsm_rst:1; 229 /** conf_upgate : WT; bitpos: [11]; default: 0; 230 * synchronization bit 231 */ 232 uint32_t conf_upgate:1; 233 uint32_t reserved_12:20; 234 }; 235 uint32_t val; 236 } lp_i2c_ctr_reg_t; 237 238 /** Type of to register 239 * Setting time out control for receiving data. 240 */ 241 typedef union { 242 struct { 243 /** time_out_value : R/W; bitpos: [4:0]; default: 16; 244 * This register is used to configure the timeout for receiving a data bit in APB 245 * clock cycles. 246 */ 247 uint32_t time_out_value:5; 248 /** time_out_en : R/W; bitpos: [5]; default: 0; 249 * This is the enable bit for time out control. 250 */ 251 uint32_t time_out_en:1; 252 uint32_t reserved_6:26; 253 }; 254 uint32_t val; 255 } lp_i2c_to_reg_t; 256 257 /** Type of fifo_conf register 258 * FIFO configuration register. 259 */ 260 typedef union { 261 struct { 262 /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6; 263 * The water mark threshold of rx FIFO in nonfifo access mode. When 264 * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than 265 * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. 266 */ 267 uint32_t rxfifo_wm_thrhd:4; 268 uint32_t reserved_4:1; 269 /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2; 270 * The water mark threshold of tx FIFO in nonfifo access mode. When 271 * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than 272 * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. 273 */ 274 uint32_t txfifo_wm_thrhd:4; 275 uint32_t reserved_9:1; 276 /** nonfifo_en : R/W; bitpos: [10]; default: 0; 277 * Set this bit to enable APB nonfifo access. 278 */ 279 uint32_t nonfifo_en:1; 280 uint32_t reserved_11:1; 281 /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; 282 * Set this bit to reset rx-fifo. 283 */ 284 uint32_t rx_fifo_rst:1; 285 /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; 286 * Set this bit to reset tx-fifo. 287 */ 288 uint32_t tx_fifo_rst:1; 289 /** fifo_prt_en : R/W; bitpos: [14]; default: 1; 290 * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls 291 * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 292 */ 293 uint32_t fifo_prt_en:1; 294 uint32_t reserved_15:17; 295 }; 296 uint32_t val; 297 } lp_i2c_fifo_conf_reg_t; 298 299 /** Type of filter_cfg register 300 * SCL and SDA filter configuration register 301 */ 302 typedef union { 303 struct { 304 /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; 305 * When a pulse on the SCL input has smaller width than this register value 306 * in I2C module clock cycles, the I2C controller will ignore that pulse. 307 */ 308 uint32_t scl_filter_thres:4; 309 /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; 310 * When a pulse on the SDA input has smaller width than this register value 311 * in I2C module clock cycles, the I2C controller will ignore that pulse. 312 */ 313 uint32_t sda_filter_thres:4; 314 /** scl_filter_en : R/W; bitpos: [8]; default: 1; 315 * This is the filter enable bit for SCL. 316 */ 317 uint32_t scl_filter_en:1; 318 /** sda_filter_en : R/W; bitpos: [9]; default: 1; 319 * This is the filter enable bit for SDA. 320 */ 321 uint32_t sda_filter_en:1; 322 uint32_t reserved_10:22; 323 }; 324 uint32_t val; 325 } lp_i2c_filter_cfg_reg_t; 326 327 /** Type of clk_conf register 328 * I2C CLK configuration register 329 */ 330 typedef union { 331 struct { 332 /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; 333 * the integral part of the fractional divisor for i2c module 334 */ 335 uint32_t sclk_div_num:8; 336 /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; 337 * the numerator of the fractional part of the fractional divisor for i2c module 338 */ 339 uint32_t sclk_div_a:6; 340 /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; 341 * the denominator of the fractional part of the fractional divisor for i2c module 342 */ 343 uint32_t sclk_div_b:6; 344 /** sclk_sel : R/W; bitpos: [20]; default: 0; 345 * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. 346 */ 347 uint32_t sclk_sel:1; 348 /** sclk_active : R/W; bitpos: [21]; default: 1; 349 * The clock switch for i2c module 350 */ 351 uint32_t sclk_active:1; 352 uint32_t reserved_22:10; 353 }; 354 uint32_t val; 355 } lp_i2c_clk_conf_reg_t; 356 357 /** Type of scl_sp_conf register 358 * Power configuration register 359 */ 360 typedef union { 361 struct { 362 /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; 363 * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses 364 * equals to reg_scl_rst_slv_num[4:0]. 365 */ 366 uint32_t scl_rst_slv_en:1; 367 /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; 368 * Configure the pulses of SCL generated in I2C master mode. Valid when 369 * reg_scl_rst_slv_en is 1. 370 */ 371 uint32_t scl_rst_slv_num:5; 372 /** scl_pd_en : R/W; bitpos: [6]; default: 0; 373 * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power 374 * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 375 */ 376 uint32_t scl_pd_en:1; 377 /** sda_pd_en : R/W; bitpos: [7]; default: 0; 378 * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power 379 * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 380 */ 381 uint32_t sda_pd_en:1; 382 uint32_t reserved_8:24; 383 }; 384 uint32_t val; 385 } lp_i2c_scl_sp_conf_reg_t; 386 387 388 /** Group: Status registers */ 389 /** Type of sr register 390 * Describe I2C work status. 391 */ 392 typedef union { 393 struct { 394 /** resp_rec : RO; bitpos: [0]; default: 0; 395 * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 396 */ 397 uint32_t resp_rec:1; 398 uint32_t reserved_1:2; 399 /** arb_lost : RO; bitpos: [3]; default: 0; 400 * When the I2C controller loses control of SCL line, this register changes to 1. 401 */ 402 uint32_t arb_lost:1; 403 /** bus_busy : RO; bitpos: [4]; default: 0; 404 * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. 405 */ 406 uint32_t bus_busy:1; 407 uint32_t reserved_5:3; 408 /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0; 409 * This field represents the amount of data needed to be sent. 410 */ 411 uint32_t rxfifo_cnt:5; 412 uint32_t reserved_13:5; 413 /** txfifo_cnt : RO; bitpos: [22:18]; default: 0; 414 * This field stores the amount of received data in RAM. 415 */ 416 uint32_t txfifo_cnt:5; 417 uint32_t reserved_23:1; 418 /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; 419 * This field indicates the states of the I2C module state machine. 420 * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: 421 * Wait ACK 422 */ 423 uint32_t scl_main_state_last:3; 424 uint32_t reserved_27:1; 425 /** scl_state_last : RO; bitpos: [30:28]; default: 0; 426 * This field indicates the states of the state machine used to produce SCL. 427 * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop 428 */ 429 uint32_t scl_state_last:3; 430 uint32_t reserved_31:1; 431 }; 432 uint32_t val; 433 } lp_i2c_sr_reg_t; 434 435 /** Type of fifo_st register 436 * FIFO status register. 437 */ 438 typedef union { 439 struct { 440 /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0; 441 * This is the offset address of the APB reading from rxfifo 442 */ 443 uint32_t rxfifo_raddr:4; 444 uint32_t reserved_4:1; 445 /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0; 446 * This is the offset address of i2c module receiving data and writing to rxfifo. 447 */ 448 uint32_t rxfifo_waddr:4; 449 uint32_t reserved_9:1; 450 /** txfifo_raddr : RO; bitpos: [13:10]; default: 0; 451 * This is the offset address of i2c module reading from txfifo. 452 */ 453 uint32_t txfifo_raddr:4; 454 uint32_t reserved_14:1; 455 /** txfifo_waddr : RO; bitpos: [18:15]; default: 0; 456 * This is the offset address of APB bus writing to txfifo. 457 */ 458 uint32_t txfifo_waddr:4; 459 uint32_t reserved_19:13; 460 }; 461 uint32_t val; 462 } lp_i2c_fifo_st_reg_t; 463 464 /** Type of data register 465 * Rx FIFO read data. 466 */ 467 typedef union { 468 struct { 469 /** fifo_rdata : RO; bitpos: [7:0]; default: 0; 470 * The value of rx FIFO read data. 471 */ 472 uint32_t fifo_rdata:8; 473 uint32_t reserved_8:24; 474 }; 475 uint32_t val; 476 } lp_i2c_data_reg_t; 477 478 479 /** Group: Interrupt registers */ 480 /** Type of int_raw register 481 * Raw interrupt status 482 */ 483 typedef union { 484 struct { 485 /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; 486 * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 487 */ 488 uint32_t rxfifo_wm_int_raw:1; 489 /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; 490 * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 491 */ 492 uint32_t txfifo_wm_int_raw:1; 493 /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; 494 * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 495 */ 496 uint32_t rxfifo_ovf_int_raw:1; 497 /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; 498 * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 499 */ 500 uint32_t end_detect_int_raw:1; 501 /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; 502 * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 503 */ 504 uint32_t byte_trans_done_int_raw:1; 505 /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; 506 * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 507 */ 508 uint32_t arbitration_lost_int_raw:1; 509 /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; 510 * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 511 */ 512 uint32_t mst_txfifo_udf_int_raw:1; 513 /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; 514 * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 515 */ 516 uint32_t trans_complete_int_raw:1; 517 /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; 518 * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 519 */ 520 uint32_t time_out_int_raw:1; 521 /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; 522 * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 523 */ 524 uint32_t trans_start_int_raw:1; 525 /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; 526 * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 527 */ 528 uint32_t nack_int_raw:1; 529 /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; 530 * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 531 */ 532 uint32_t txfifo_ovf_int_raw:1; 533 /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; 534 * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 535 */ 536 uint32_t rxfifo_udf_int_raw:1; 537 /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; 538 * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 539 */ 540 uint32_t scl_st_to_int_raw:1; 541 /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; 542 * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 543 */ 544 uint32_t scl_main_st_to_int_raw:1; 545 /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; 546 * The raw interrupt bit for I2C_DET_START_INT interrupt. 547 */ 548 uint32_t det_start_int_raw:1; 549 uint32_t reserved_16:16; 550 }; 551 uint32_t val; 552 } lp_i2c_int_raw_reg_t; 553 554 /** Type of int_clr register 555 * Interrupt clear bits 556 */ 557 typedef union { 558 struct { 559 /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; 560 * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 561 */ 562 uint32_t rxfifo_wm_int_clr:1; 563 /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; 564 * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 565 */ 566 uint32_t txfifo_wm_int_clr:1; 567 /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; 568 * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 569 */ 570 uint32_t rxfifo_ovf_int_clr:1; 571 /** end_detect_int_clr : WT; bitpos: [3]; default: 0; 572 * Set this bit to clear the I2C_END_DETECT_INT interrupt. 573 */ 574 uint32_t end_detect_int_clr:1; 575 /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; 576 * Set this bit to clear the I2C_END_DETECT_INT interrupt. 577 */ 578 uint32_t byte_trans_done_int_clr:1; 579 /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; 580 * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 581 */ 582 uint32_t arbitration_lost_int_clr:1; 583 /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; 584 * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 585 */ 586 uint32_t mst_txfifo_udf_int_clr:1; 587 /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; 588 * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 589 */ 590 uint32_t trans_complete_int_clr:1; 591 /** time_out_int_clr : WT; bitpos: [8]; default: 0; 592 * Set this bit to clear the I2C_TIME_OUT_INT interrupt. 593 */ 594 uint32_t time_out_int_clr:1; 595 /** trans_start_int_clr : WT; bitpos: [9]; default: 0; 596 * Set this bit to clear the I2C_TRANS_START_INT interrupt. 597 */ 598 uint32_t trans_start_int_clr:1; 599 /** nack_int_clr : WT; bitpos: [10]; default: 0; 600 * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 601 */ 602 uint32_t nack_int_clr:1; 603 /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; 604 * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 605 */ 606 uint32_t txfifo_ovf_int_clr:1; 607 /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; 608 * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 609 */ 610 uint32_t rxfifo_udf_int_clr:1; 611 /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; 612 * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 613 */ 614 uint32_t scl_st_to_int_clr:1; 615 /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; 616 * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 617 */ 618 uint32_t scl_main_st_to_int_clr:1; 619 /** det_start_int_clr : WT; bitpos: [15]; default: 0; 620 * Set this bit to clear I2C_DET_START_INT interrupt. 621 */ 622 uint32_t det_start_int_clr:1; 623 uint32_t reserved_16:16; 624 }; 625 uint32_t val; 626 } lp_i2c_int_clr_reg_t; 627 628 /** Type of int_ena register 629 * Interrupt enable bits 630 */ 631 typedef union { 632 struct { 633 /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; 634 * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. 635 */ 636 uint32_t rxfifo_wm_int_ena:1; 637 /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; 638 * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. 639 */ 640 uint32_t txfifo_wm_int_ena:1; 641 /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; 642 * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. 643 */ 644 uint32_t rxfifo_ovf_int_ena:1; 645 /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; 646 * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 647 */ 648 uint32_t end_detect_int_ena:1; 649 /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; 650 * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 651 */ 652 uint32_t byte_trans_done_int_ena:1; 653 /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; 654 * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. 655 */ 656 uint32_t arbitration_lost_int_ena:1; 657 /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; 658 * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. 659 */ 660 uint32_t mst_txfifo_udf_int_ena:1; 661 /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; 662 * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. 663 */ 664 uint32_t trans_complete_int_ena:1; 665 /** time_out_int_ena : R/W; bitpos: [8]; default: 0; 666 * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. 667 */ 668 uint32_t time_out_int_ena:1; 669 /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; 670 * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. 671 */ 672 uint32_t trans_start_int_ena:1; 673 /** nack_int_ena : R/W; bitpos: [10]; default: 0; 674 * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 675 */ 676 uint32_t nack_int_ena:1; 677 /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; 678 * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. 679 */ 680 uint32_t txfifo_ovf_int_ena:1; 681 /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; 682 * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. 683 */ 684 uint32_t rxfifo_udf_int_ena:1; 685 /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; 686 * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. 687 */ 688 uint32_t scl_st_to_int_ena:1; 689 /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; 690 * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 691 */ 692 uint32_t scl_main_st_to_int_ena:1; 693 /** det_start_int_ena : R/W; bitpos: [15]; default: 0; 694 * The interrupt enable bit for I2C_DET_START_INT interrupt. 695 */ 696 uint32_t det_start_int_ena:1; 697 uint32_t reserved_16:16; 698 }; 699 uint32_t val; 700 } lp_i2c_int_ena_reg_t; 701 702 /** Type of int_status register 703 * Status of captured I2C communication events 704 */ 705 typedef union { 706 struct { 707 /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; 708 * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 709 */ 710 uint32_t rxfifo_wm_int_st:1; 711 /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; 712 * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 713 */ 714 uint32_t txfifo_wm_int_st:1; 715 /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; 716 * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 717 */ 718 uint32_t rxfifo_ovf_int_st:1; 719 /** end_detect_int_st : RO; bitpos: [3]; default: 0; 720 * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 721 */ 722 uint32_t end_detect_int_st:1; 723 /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; 724 * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 725 */ 726 uint32_t byte_trans_done_int_st:1; 727 /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; 728 * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 729 */ 730 uint32_t arbitration_lost_int_st:1; 731 /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; 732 * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 733 */ 734 uint32_t mst_txfifo_udf_int_st:1; 735 /** trans_complete_int_st : RO; bitpos: [7]; default: 0; 736 * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 737 */ 738 uint32_t trans_complete_int_st:1; 739 /** time_out_int_st : RO; bitpos: [8]; default: 0; 740 * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 741 */ 742 uint32_t time_out_int_st:1; 743 /** trans_start_int_st : RO; bitpos: [9]; default: 0; 744 * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 745 */ 746 uint32_t trans_start_int_st:1; 747 /** nack_int_st : RO; bitpos: [10]; default: 0; 748 * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 749 */ 750 uint32_t nack_int_st:1; 751 /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; 752 * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 753 */ 754 uint32_t txfifo_ovf_int_st:1; 755 /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; 756 * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 757 */ 758 uint32_t rxfifo_udf_int_st:1; 759 /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; 760 * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 761 */ 762 uint32_t scl_st_to_int_st:1; 763 /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; 764 * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 765 */ 766 uint32_t scl_main_st_to_int_st:1; 767 /** det_start_int_st : RO; bitpos: [15]; default: 0; 768 * The masked interrupt status bit for I2C_DET_START_INT interrupt. 769 */ 770 uint32_t det_start_int_st:1; 771 uint32_t reserved_16:16; 772 }; 773 uint32_t val; 774 } lp_i2c_int_status_reg_t; 775 776 777 /** Group: Command registers */ 778 /** Type of command register 779 * I2C command register 780 */ 781 typedef union { 782 struct { 783 /** command : R/W; bitpos: [13:0]; default: 0; 784 * This is the content of a command. It consists of three parts: 785 * op_code is the command, 6: RSTART, 1: WRITE, 3: READ, 2: STOP, 4: END. 786 * Byte_num represents the number of bytes that need to be sent or received. 787 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 788 * structure for more information. 789 */ 790 uint32_t byte_num:8; 791 uint32_t ack_en:1; 792 uint32_t ack_exp:1; 793 uint32_t ack_val:1; 794 uint32_t op_code:3; 795 uint32_t reserved_14:17; 796 /** command_done : R/W/SS; bitpos: [31]; default: 0; 797 * When command is done in I2C Master mode, this bit changes to high 798 * level. 799 */ 800 uint32_t command_done:1; 801 }; 802 uint32_t val; 803 } lp_i2c_command_reg_t; 804 805 806 /** Group: Version register */ 807 /** Type of date register 808 * Version register 809 */ 810 typedef union { 811 struct { 812 /** date : R/W; bitpos: [31:0]; default: 35656003; 813 * This is the the version register. 814 */ 815 uint32_t date:32; 816 }; 817 uint32_t val; 818 } lp_i2c_date_reg_t; 819 820 821 /** Group: Address register */ 822 /** Type of txfifo_start_addr register 823 * I2C TXFIFO base address register 824 */ 825 typedef union { 826 struct { 827 /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; 828 * This is the I2C txfifo first address. 829 */ 830 uint32_t txfifo_start_addr:32; 831 }; 832 uint32_t val; 833 } lp_i2c_txfifo_start_addr_reg_t; 834 835 /** Type of rxfifo_start_addr register 836 * I2C RXFIFO base address register 837 */ 838 typedef union { 839 struct { 840 /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; 841 * This is the I2C rxfifo first address. 842 */ 843 uint32_t rxfifo_start_addr:32; 844 }; 845 uint32_t val; 846 } lp_i2c_rxfifo_start_addr_reg_t; 847 848 849 typedef struct lp_i2c_dev_t { 850 volatile lp_i2c_scl_low_period_reg_t scl_low_period; 851 volatile lp_i2c_ctr_reg_t ctr; 852 volatile lp_i2c_sr_reg_t sr; 853 volatile lp_i2c_to_reg_t to; 854 uint32_t reserved_010; 855 volatile lp_i2c_fifo_st_reg_t fifo_st; 856 volatile lp_i2c_fifo_conf_reg_t fifo_conf; 857 volatile lp_i2c_data_reg_t data; 858 volatile lp_i2c_int_raw_reg_t int_raw; 859 volatile lp_i2c_int_clr_reg_t int_clr; 860 volatile lp_i2c_int_ena_reg_t int_ena; 861 volatile lp_i2c_int_status_reg_t int_status; 862 volatile lp_i2c_sda_hold_reg_t sda_hold; 863 volatile lp_i2c_sda_sample_reg_t sda_sample; 864 volatile lp_i2c_scl_high_period_reg_t scl_high_period; 865 uint32_t reserved_03c; 866 volatile lp_i2c_scl_start_hold_reg_t scl_start_hold; 867 volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup; 868 volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold; 869 volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup; 870 volatile lp_i2c_filter_cfg_reg_t filter_cfg; 871 volatile lp_i2c_clk_conf_reg_t clk_conf; 872 volatile lp_i2c_command_reg_t command[8]; 873 volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out; 874 volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; 875 volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf; 876 uint32_t reserved_084[29]; 877 volatile lp_i2c_date_reg_t date; 878 uint32_t reserved_0fc; 879 volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr; 880 uint32_t reserved_104[31]; 881 volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; 882 } lp_i2c_dev_t; 883 884 // We map the LP_I2C instance to the i2c_dev_t struct for convinience of using the same HAL/LL. See soc/i2c_struct.h 885 //extern lp_i2c_dev_t LP_I2C; 886 887 #ifndef __cplusplus 888 _Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure"); 889 #endif 890 891 #ifdef __cplusplus 892 } 893 #endif 894
