1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_I2C_SCL_LOW_PERIOD_REG register 15 * Configures the low level width of the SCL 16 * Clock 17 */ 18 #define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) 19 /** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; 20 * This register is used to configure for how long SCL remains low in master mode, in 21 * I2C module clock cycles. 22 */ 23 #define LP_I2C_SCL_LOW_PERIOD 0x000001FFU 24 #define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) 25 #define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU 26 #define LP_I2C_SCL_LOW_PERIOD_S 0 27 28 /** LP_I2C_CTR_REG register 29 * Transmission setting 30 */ 31 #define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) 32 /** LP_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; 33 * 1: direct output, 0: open drain output. 34 */ 35 #define LP_I2C_SDA_FORCE_OUT (BIT(0)) 36 #define LP_I2C_SDA_FORCE_OUT_M (LP_I2C_SDA_FORCE_OUT_V << LP_I2C_SDA_FORCE_OUT_S) 37 #define LP_I2C_SDA_FORCE_OUT_V 0x00000001U 38 #define LP_I2C_SDA_FORCE_OUT_S 0 39 /** LP_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; 40 * 1: direct output, 0: open drain output. 41 */ 42 #define LP_I2C_SCL_FORCE_OUT (BIT(1)) 43 #define LP_I2C_SCL_FORCE_OUT_M (LP_I2C_SCL_FORCE_OUT_V << LP_I2C_SCL_FORCE_OUT_S) 44 #define LP_I2C_SCL_FORCE_OUT_V 0x00000001U 45 #define LP_I2C_SCL_FORCE_OUT_S 1 46 /** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; 47 * This register is used to select the sample mode. 48 * 1: sample SDA data on the SCL low level. 49 * 0: sample SDA data on the SCL high level. 50 */ 51 #define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) 52 #define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) 53 #define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U 54 #define LP_I2C_SAMPLE_SCL_LEVEL_S 2 55 /** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; 56 * This register is used to configure the ACK value that need to sent by master when 57 * the rx_fifo_cnt has reached the threshold. 58 */ 59 #define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) 60 #define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) 61 #define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U 62 #define LP_I2C_RX_FULL_ACK_LEVEL_S 3 63 /** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; 64 * Set this bit to start sending the data in txfifo. 65 */ 66 #define LP_I2C_TRANS_START (BIT(5)) 67 #define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) 68 #define LP_I2C_TRANS_START_V 0x00000001U 69 #define LP_I2C_TRANS_START_S 5 70 /** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; 71 * This bit is used to control the sending mode for data needing to be sent. 72 * 1: send data from the least significant bit, 73 * 0: send data from the most significant bit. 74 */ 75 #define LP_I2C_TX_LSB_FIRST (BIT(6)) 76 #define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) 77 #define LP_I2C_TX_LSB_FIRST_V 0x00000001U 78 #define LP_I2C_TX_LSB_FIRST_S 6 79 /** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; 80 * This bit is used to control the storage mode for received data. 81 * 1: receive data from the least significant bit, 82 * 0: receive data from the most significant bit. 83 */ 84 #define LP_I2C_RX_LSB_FIRST (BIT(7)) 85 #define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) 86 #define LP_I2C_RX_LSB_FIRST_V 0x00000001U 87 #define LP_I2C_RX_LSB_FIRST_S 7 88 /** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; 89 * Reserved 90 */ 91 #define LP_I2C_CLK_EN (BIT(8)) 92 #define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) 93 #define LP_I2C_CLK_EN_V 0x00000001U 94 #define LP_I2C_CLK_EN_S 8 95 /** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; 96 * This is the enable bit for arbitration_lost. 97 */ 98 #define LP_I2C_ARBITRATION_EN (BIT(9)) 99 #define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) 100 #define LP_I2C_ARBITRATION_EN_V 0x00000001U 101 #define LP_I2C_ARBITRATION_EN_S 9 102 /** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; 103 * This register is used to reset the scl FMS. 104 */ 105 #define LP_I2C_FSM_RST (BIT(10)) 106 #define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) 107 #define LP_I2C_FSM_RST_V 0x00000001U 108 #define LP_I2C_FSM_RST_S 10 109 /** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; 110 * synchronization bit 111 */ 112 #define LP_I2C_CONF_UPGATE (BIT(11)) 113 #define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) 114 #define LP_I2C_CONF_UPGATE_V 0x00000001U 115 #define LP_I2C_CONF_UPGATE_S 11 116 117 /** LP_I2C_SR_REG register 118 * Describe I2C work status. 119 */ 120 #define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) 121 /** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; 122 * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 123 */ 124 #define LP_I2C_RESP_REC (BIT(0)) 125 #define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) 126 #define LP_I2C_RESP_REC_V 0x00000001U 127 #define LP_I2C_RESP_REC_S 0 128 /** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; 129 * When the I2C controller loses control of SCL line, this register changes to 1. 130 */ 131 #define LP_I2C_ARB_LOST (BIT(3)) 132 #define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) 133 #define LP_I2C_ARB_LOST_V 0x00000001U 134 #define LP_I2C_ARB_LOST_S 3 135 /** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; 136 * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. 137 */ 138 #define LP_I2C_BUS_BUSY (BIT(4)) 139 #define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) 140 #define LP_I2C_BUS_BUSY_V 0x00000001U 141 #define LP_I2C_BUS_BUSY_S 4 142 /** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; 143 * This field represents the amount of data needed to be sent. 144 */ 145 #define LP_I2C_RXFIFO_CNT 0x0000001FU 146 #define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) 147 #define LP_I2C_RXFIFO_CNT_V 0x0000001FU 148 #define LP_I2C_RXFIFO_CNT_S 8 149 /** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; 150 * This field stores the amount of received data in RAM. 151 */ 152 #define LP_I2C_TXFIFO_CNT 0x0000001FU 153 #define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) 154 #define LP_I2C_TXFIFO_CNT_V 0x0000001FU 155 #define LP_I2C_TXFIFO_CNT_S 18 156 /** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; 157 * This field indicates the states of the I2C module state machine. 158 * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: 159 * Wait ACK 160 */ 161 #define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U 162 #define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) 163 #define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U 164 #define LP_I2C_SCL_MAIN_STATE_LAST_S 24 165 /** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; 166 * This field indicates the states of the state machine used to produce SCL. 167 * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop 168 */ 169 #define LP_I2C_SCL_STATE_LAST 0x00000007U 170 #define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) 171 #define LP_I2C_SCL_STATE_LAST_V 0x00000007U 172 #define LP_I2C_SCL_STATE_LAST_S 28 173 174 /** LP_I2C_TO_REG register 175 * Setting time out control for receiving data. 176 */ 177 #define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) 178 /** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; 179 * This register is used to configure the timeout for receiving a data bit in APB 180 * clock cycles. 181 */ 182 #define LP_I2C_TIME_OUT_VALUE 0x0000001FU 183 #define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) 184 #define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU 185 #define LP_I2C_TIME_OUT_VALUE_S 0 186 /** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; 187 * This is the enable bit for time out control. 188 */ 189 #define LP_I2C_TIME_OUT_EN (BIT(5)) 190 #define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) 191 #define LP_I2C_TIME_OUT_EN_V 0x00000001U 192 #define LP_I2C_TIME_OUT_EN_S 5 193 194 /** LP_I2C_FIFO_ST_REG register 195 * FIFO status register. 196 */ 197 #define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) 198 /** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; 199 * This is the offset address of the APB reading from rxfifo 200 */ 201 #define LP_I2C_RXFIFO_RADDR 0x0000000FU 202 #define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) 203 #define LP_I2C_RXFIFO_RADDR_V 0x0000000FU 204 #define LP_I2C_RXFIFO_RADDR_S 0 205 /** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; 206 * This is the offset address of i2c module receiving data and writing to rxfifo. 207 */ 208 #define LP_I2C_RXFIFO_WADDR 0x0000000FU 209 #define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) 210 #define LP_I2C_RXFIFO_WADDR_V 0x0000000FU 211 #define LP_I2C_RXFIFO_WADDR_S 5 212 /** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; 213 * This is the offset address of i2c module reading from txfifo. 214 */ 215 #define LP_I2C_TXFIFO_RADDR 0x0000000FU 216 #define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) 217 #define LP_I2C_TXFIFO_RADDR_V 0x0000000FU 218 #define LP_I2C_TXFIFO_RADDR_S 10 219 /** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; 220 * This is the offset address of APB bus writing to txfifo. 221 */ 222 #define LP_I2C_TXFIFO_WADDR 0x0000000FU 223 #define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) 224 #define LP_I2C_TXFIFO_WADDR_V 0x0000000FU 225 #define LP_I2C_TXFIFO_WADDR_S 15 226 227 /** LP_I2C_FIFO_CONF_REG register 228 * FIFO configuration register. 229 */ 230 #define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) 231 /** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; 232 * The water mark threshold of rx FIFO in nonfifo access mode. When 233 * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than 234 * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. 235 */ 236 #define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU 237 #define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) 238 #define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU 239 #define LP_I2C_RXFIFO_WM_THRHD_S 0 240 /** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; 241 * The water mark threshold of tx FIFO in nonfifo access mode. When 242 * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than 243 * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. 244 */ 245 #define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU 246 #define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) 247 #define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU 248 #define LP_I2C_TXFIFO_WM_THRHD_S 5 249 /** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; 250 * Set this bit to enable APB nonfifo access. 251 */ 252 #define LP_I2C_NONFIFO_EN (BIT(10)) 253 #define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) 254 #define LP_I2C_NONFIFO_EN_V 0x00000001U 255 #define LP_I2C_NONFIFO_EN_S 10 256 /** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; 257 * Set this bit to reset rx-fifo. 258 */ 259 #define LP_I2C_RX_FIFO_RST (BIT(12)) 260 #define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) 261 #define LP_I2C_RX_FIFO_RST_V 0x00000001U 262 #define LP_I2C_RX_FIFO_RST_S 12 263 /** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; 264 * Set this bit to reset tx-fifo. 265 */ 266 #define LP_I2C_TX_FIFO_RST (BIT(13)) 267 #define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) 268 #define LP_I2C_TX_FIFO_RST_V 0x00000001U 269 #define LP_I2C_TX_FIFO_RST_S 13 270 /** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; 271 * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls 272 * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 273 */ 274 #define LP_I2C_FIFO_PRT_EN (BIT(14)) 275 #define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) 276 #define LP_I2C_FIFO_PRT_EN_V 0x00000001U 277 #define LP_I2C_FIFO_PRT_EN_S 14 278 279 /** LP_I2C_DATA_REG register 280 * Rx FIFO read data. 281 */ 282 #define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) 283 /** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; 284 * The value of rx FIFO read data. 285 */ 286 #define LP_I2C_FIFO_RDATA 0x000000FFU 287 #define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) 288 #define LP_I2C_FIFO_RDATA_V 0x000000FFU 289 #define LP_I2C_FIFO_RDATA_S 0 290 291 /** LP_I2C_INT_RAW_REG register 292 * Raw interrupt status 293 */ 294 #define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) 295 /** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; 296 * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. 297 */ 298 #define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) 299 #define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) 300 #define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U 301 #define LP_I2C_RXFIFO_WM_INT_RAW_S 0 302 /** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; 303 * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. 304 */ 305 #define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) 306 #define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) 307 #define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U 308 #define LP_I2C_TXFIFO_WM_INT_RAW_S 1 309 /** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; 310 * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. 311 */ 312 #define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) 313 #define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) 314 #define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U 315 #define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 316 /** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; 317 * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. 318 */ 319 #define LP_I2C_END_DETECT_INT_RAW (BIT(3)) 320 #define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) 321 #define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U 322 #define LP_I2C_END_DETECT_INT_RAW_S 3 323 /** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; 324 * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. 325 */ 326 #define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) 327 #define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) 328 #define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U 329 #define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 330 /** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; 331 * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. 332 */ 333 #define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) 334 #define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) 335 #define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U 336 #define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 337 /** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; 338 * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. 339 */ 340 #define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) 341 #define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) 342 #define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U 343 #define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 344 /** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; 345 * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. 346 */ 347 #define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) 348 #define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) 349 #define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U 350 #define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 351 /** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; 352 * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. 353 */ 354 #define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) 355 #define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) 356 #define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U 357 #define LP_I2C_TIME_OUT_INT_RAW_S 8 358 /** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; 359 * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. 360 */ 361 #define LP_I2C_TRANS_START_INT_RAW (BIT(9)) 362 #define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) 363 #define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U 364 #define LP_I2C_TRANS_START_INT_RAW_S 9 365 /** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; 366 * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. 367 */ 368 #define LP_I2C_NACK_INT_RAW (BIT(10)) 369 #define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) 370 #define LP_I2C_NACK_INT_RAW_V 0x00000001U 371 #define LP_I2C_NACK_INT_RAW_S 10 372 /** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; 373 * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. 374 */ 375 #define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) 376 #define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) 377 #define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U 378 #define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 379 /** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; 380 * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. 381 */ 382 #define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) 383 #define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) 384 #define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U 385 #define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 386 /** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; 387 * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. 388 */ 389 #define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) 390 #define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) 391 #define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U 392 #define LP_I2C_SCL_ST_TO_INT_RAW_S 13 393 /** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; 394 * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. 395 */ 396 #define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) 397 #define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) 398 #define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U 399 #define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 400 /** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; 401 * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. 402 */ 403 #define LP_I2C_DET_START_INT_RAW (BIT(15)) 404 #define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) 405 #define LP_I2C_DET_START_INT_RAW_V 0x00000001U 406 #define LP_I2C_DET_START_INT_RAW_S 15 407 408 /** LP_I2C_INT_CLR_REG register 409 * Interrupt clear bits 410 */ 411 #define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) 412 /** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; 413 * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. 414 */ 415 #define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) 416 #define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) 417 #define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U 418 #define LP_I2C_RXFIFO_WM_INT_CLR_S 0 419 /** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; 420 * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. 421 */ 422 #define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) 423 #define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) 424 #define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U 425 #define LP_I2C_TXFIFO_WM_INT_CLR_S 1 426 /** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; 427 * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. 428 */ 429 #define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) 430 #define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) 431 #define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U 432 #define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 433 /** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; 434 * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. 435 */ 436 #define LP_I2C_END_DETECT_INT_CLR (BIT(3)) 437 #define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) 438 #define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U 439 #define LP_I2C_END_DETECT_INT_CLR_S 3 440 /** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; 441 * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. 442 */ 443 #define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) 444 #define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) 445 #define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U 446 #define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 447 /** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; 448 * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. 449 */ 450 #define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) 451 #define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) 452 #define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U 453 #define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 454 /** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; 455 * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. 456 */ 457 #define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) 458 #define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) 459 #define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U 460 #define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 461 /** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; 462 * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. 463 */ 464 #define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) 465 #define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) 466 #define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U 467 #define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 468 /** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; 469 * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. 470 */ 471 #define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) 472 #define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) 473 #define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U 474 #define LP_I2C_TIME_OUT_INT_CLR_S 8 475 /** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; 476 * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. 477 */ 478 #define LP_I2C_TRANS_START_INT_CLR (BIT(9)) 479 #define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) 480 #define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U 481 #define LP_I2C_TRANS_START_INT_CLR_S 9 482 /** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; 483 * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. 484 */ 485 #define LP_I2C_NACK_INT_CLR (BIT(10)) 486 #define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) 487 #define LP_I2C_NACK_INT_CLR_V 0x00000001U 488 #define LP_I2C_NACK_INT_CLR_S 10 489 /** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; 490 * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. 491 */ 492 #define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) 493 #define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) 494 #define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U 495 #define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 496 /** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; 497 * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. 498 */ 499 #define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) 500 #define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) 501 #define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U 502 #define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 503 /** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; 504 * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. 505 */ 506 #define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) 507 #define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) 508 #define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U 509 #define LP_I2C_SCL_ST_TO_INT_CLR_S 13 510 /** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; 511 * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. 512 */ 513 #define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) 514 #define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) 515 #define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U 516 #define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 517 /** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; 518 * Set this bit to clear LP_I2C_DET_START_INT interrupt. 519 */ 520 #define LP_I2C_DET_START_INT_CLR (BIT(15)) 521 #define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) 522 #define LP_I2C_DET_START_INT_CLR_V 0x00000001U 523 #define LP_I2C_DET_START_INT_CLR_S 15 524 525 /** LP_I2C_INT_ENA_REG register 526 * Interrupt enable bits 527 */ 528 #define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) 529 /** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; 530 * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. 531 */ 532 #define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) 533 #define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) 534 #define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U 535 #define LP_I2C_RXFIFO_WM_INT_ENA_S 0 536 /** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; 537 * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. 538 */ 539 #define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) 540 #define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) 541 #define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U 542 #define LP_I2C_TXFIFO_WM_INT_ENA_S 1 543 /** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; 544 * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. 545 */ 546 #define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) 547 #define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) 548 #define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U 549 #define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 550 /** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; 551 * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. 552 */ 553 #define LP_I2C_END_DETECT_INT_ENA (BIT(3)) 554 #define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) 555 #define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U 556 #define LP_I2C_END_DETECT_INT_ENA_S 3 557 /** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; 558 * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. 559 */ 560 #define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) 561 #define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) 562 #define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U 563 #define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 564 /** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; 565 * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. 566 */ 567 #define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) 568 #define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) 569 #define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U 570 #define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 571 /** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; 572 * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. 573 */ 574 #define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) 575 #define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) 576 #define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U 577 #define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 578 /** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; 579 * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. 580 */ 581 #define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) 582 #define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) 583 #define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U 584 #define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 585 /** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; 586 * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. 587 */ 588 #define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) 589 #define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) 590 #define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U 591 #define LP_I2C_TIME_OUT_INT_ENA_S 8 592 /** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; 593 * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. 594 */ 595 #define LP_I2C_TRANS_START_INT_ENA (BIT(9)) 596 #define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) 597 #define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U 598 #define LP_I2C_TRANS_START_INT_ENA_S 9 599 /** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; 600 * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. 601 */ 602 #define LP_I2C_NACK_INT_ENA (BIT(10)) 603 #define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) 604 #define LP_I2C_NACK_INT_ENA_V 0x00000001U 605 #define LP_I2C_NACK_INT_ENA_S 10 606 /** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; 607 * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. 608 */ 609 #define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) 610 #define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) 611 #define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U 612 #define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 613 /** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; 614 * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. 615 */ 616 #define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) 617 #define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) 618 #define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U 619 #define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 620 /** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; 621 * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. 622 */ 623 #define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) 624 #define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) 625 #define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U 626 #define LP_I2C_SCL_ST_TO_INT_ENA_S 13 627 /** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; 628 * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. 629 */ 630 #define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) 631 #define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) 632 #define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U 633 #define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 634 /** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; 635 * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. 636 */ 637 #define LP_I2C_DET_START_INT_ENA (BIT(15)) 638 #define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) 639 #define LP_I2C_DET_START_INT_ENA_V 0x00000001U 640 #define LP_I2C_DET_START_INT_ENA_S 15 641 642 /** LP_I2C_INT_STATUS_REG register 643 * Status of captured I2C communication events 644 */ 645 #define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) 646 /** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; 647 * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. 648 */ 649 #define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) 650 #define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) 651 #define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U 652 #define LP_I2C_RXFIFO_WM_INT_ST_S 0 653 /** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; 654 * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. 655 */ 656 #define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) 657 #define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) 658 #define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U 659 #define LP_I2C_TXFIFO_WM_INT_ST_S 1 660 /** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; 661 * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. 662 */ 663 #define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) 664 #define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) 665 #define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U 666 #define LP_I2C_RXFIFO_OVF_INT_ST_S 2 667 /** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; 668 * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. 669 */ 670 #define LP_I2C_END_DETECT_INT_ST (BIT(3)) 671 #define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) 672 #define LP_I2C_END_DETECT_INT_ST_V 0x00000001U 673 #define LP_I2C_END_DETECT_INT_ST_S 3 674 /** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; 675 * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. 676 */ 677 #define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) 678 #define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) 679 #define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U 680 #define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 681 /** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; 682 * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. 683 */ 684 #define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) 685 #define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) 686 #define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U 687 #define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 688 /** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; 689 * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. 690 */ 691 #define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) 692 #define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) 693 #define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U 694 #define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 695 /** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; 696 * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. 697 */ 698 #define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) 699 #define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) 700 #define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U 701 #define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 702 /** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; 703 * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. 704 */ 705 #define LP_I2C_TIME_OUT_INT_ST (BIT(8)) 706 #define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) 707 #define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U 708 #define LP_I2C_TIME_OUT_INT_ST_S 8 709 /** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; 710 * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. 711 */ 712 #define LP_I2C_TRANS_START_INT_ST (BIT(9)) 713 #define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) 714 #define LP_I2C_TRANS_START_INT_ST_V 0x00000001U 715 #define LP_I2C_TRANS_START_INT_ST_S 9 716 /** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; 717 * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. 718 */ 719 #define LP_I2C_NACK_INT_ST (BIT(10)) 720 #define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) 721 #define LP_I2C_NACK_INT_ST_V 0x00000001U 722 #define LP_I2C_NACK_INT_ST_S 10 723 /** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; 724 * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. 725 */ 726 #define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) 727 #define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) 728 #define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U 729 #define LP_I2C_TXFIFO_OVF_INT_ST_S 11 730 /** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; 731 * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. 732 */ 733 #define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) 734 #define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) 735 #define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U 736 #define LP_I2C_RXFIFO_UDF_INT_ST_S 12 737 /** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; 738 * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. 739 */ 740 #define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) 741 #define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) 742 #define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U 743 #define LP_I2C_SCL_ST_TO_INT_ST_S 13 744 /** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; 745 * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. 746 */ 747 #define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) 748 #define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) 749 #define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U 750 #define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 751 /** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; 752 * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. 753 */ 754 #define LP_I2C_DET_START_INT_ST (BIT(15)) 755 #define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) 756 #define LP_I2C_DET_START_INT_ST_V 0x00000001U 757 #define LP_I2C_DET_START_INT_ST_S 15 758 759 /** LP_I2C_SDA_HOLD_REG register 760 * Configures the hold time after a negative SCL edge. 761 */ 762 #define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) 763 /** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; 764 * This register is used to configure the time to hold the data after the negative 765 * edge of SCL, in I2C module clock cycles. 766 */ 767 #define LP_I2C_SDA_HOLD_TIME 0x000001FFU 768 #define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) 769 #define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU 770 #define LP_I2C_SDA_HOLD_TIME_S 0 771 772 /** LP_I2C_SDA_SAMPLE_REG register 773 * Configures the sample time after a positive SCL edge. 774 */ 775 #define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) 776 /** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; 777 * This register is used to configure for how long SDA is sampled, in I2C module clock 778 * cycles. 779 */ 780 #define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU 781 #define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) 782 #define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU 783 #define LP_I2C_SDA_SAMPLE_TIME_S 0 784 785 /** LP_I2C_SCL_HIGH_PERIOD_REG register 786 * Configures the high level width of SCL 787 */ 788 #define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) 789 /** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; 790 * This register is used to configure for how long SCL setup to high level and remains 791 * high in master mode, in I2C module clock cycles. 792 */ 793 #define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU 794 #define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) 795 #define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU 796 #define LP_I2C_SCL_HIGH_PERIOD_S 0 797 /** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; 798 * This register is used to configure for the SCL_FSM's waiting period for SCL high 799 * level in master mode, in I2C module clock cycles. 800 */ 801 #define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU 802 #define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) 803 #define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU 804 #define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 805 806 /** LP_I2C_SCL_START_HOLD_REG register 807 * Configures the delay between the SDA and SCL negative edge for a start condition 808 */ 809 #define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) 810 /** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; 811 * This register is used to configure the time between the negative edge 812 * of SDA and the negative edge of SCL for a START condition, in I2C module clock 813 * cycles. 814 */ 815 #define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU 816 #define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) 817 #define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU 818 #define LP_I2C_SCL_START_HOLD_TIME_S 0 819 820 /** LP_I2C_SCL_RSTART_SETUP_REG register 821 * Configures the delay between the positive 822 * edge of SCL and the negative edge of SDA 823 */ 824 #define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) 825 /** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; 826 * This register is used to configure the time between the positive 827 * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module 828 * clock cycles. 829 */ 830 #define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU 831 #define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) 832 #define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU 833 #define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 834 835 /** LP_I2C_SCL_STOP_HOLD_REG register 836 * Configures the delay after the SCL clock 837 * edge for a stop condition 838 */ 839 #define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) 840 /** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; 841 * This register is used to configure the delay after the STOP condition, 842 * in I2C module clock cycles. 843 */ 844 #define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU 845 #define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) 846 #define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU 847 #define LP_I2C_SCL_STOP_HOLD_TIME_S 0 848 849 /** LP_I2C_SCL_STOP_SETUP_REG register 850 * Configures the delay between the SDA and 851 * SCL positive edge for a stop condition 852 */ 853 #define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) 854 /** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; 855 * This register is used to configure the time between the positive edge 856 * of SCL and the positive edge of SDA, in I2C module clock cycles. 857 */ 858 #define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU 859 #define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) 860 #define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU 861 #define LP_I2C_SCL_STOP_SETUP_TIME_S 0 862 863 /** LP_I2C_FILTER_CFG_REG register 864 * SCL and SDA filter configuration register 865 */ 866 #define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) 867 /** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; 868 * When a pulse on the SCL input has smaller width than this register value 869 * in I2C module clock cycles, the I2C controller will ignore that pulse. 870 */ 871 #define LP_I2C_SCL_FILTER_THRES 0x0000000FU 872 #define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) 873 #define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU 874 #define LP_I2C_SCL_FILTER_THRES_S 0 875 /** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; 876 * When a pulse on the SDA input has smaller width than this register value 877 * in I2C module clock cycles, the I2C controller will ignore that pulse. 878 */ 879 #define LP_I2C_SDA_FILTER_THRES 0x0000000FU 880 #define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) 881 #define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU 882 #define LP_I2C_SDA_FILTER_THRES_S 4 883 /** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; 884 * This is the filter enable bit for SCL. 885 */ 886 #define LP_I2C_SCL_FILTER_EN (BIT(8)) 887 #define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) 888 #define LP_I2C_SCL_FILTER_EN_V 0x00000001U 889 #define LP_I2C_SCL_FILTER_EN_S 8 890 /** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; 891 * This is the filter enable bit for SDA. 892 */ 893 #define LP_I2C_SDA_FILTER_EN (BIT(9)) 894 #define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) 895 #define LP_I2C_SDA_FILTER_EN_V 0x00000001U 896 #define LP_I2C_SDA_FILTER_EN_S 9 897 898 /** LP_I2C_CLK_CONF_REG register 899 * I2C CLK configuration register 900 */ 901 #define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) 902 /** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; 903 * the integral part of the fractional divisor for i2c module 904 */ 905 #define LP_I2C_SCLK_DIV_NUM 0x000000FFU 906 #define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) 907 #define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU 908 #define LP_I2C_SCLK_DIV_NUM_S 0 909 /** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; 910 * the numerator of the fractional part of the fractional divisor for i2c module 911 */ 912 #define LP_I2C_SCLK_DIV_A 0x0000003FU 913 #define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) 914 #define LP_I2C_SCLK_DIV_A_V 0x0000003FU 915 #define LP_I2C_SCLK_DIV_A_S 8 916 /** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; 917 * the denominator of the fractional part of the fractional divisor for i2c module 918 */ 919 #define LP_I2C_SCLK_DIV_B 0x0000003FU 920 #define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) 921 #define LP_I2C_SCLK_DIV_B_V 0x0000003FU 922 #define LP_I2C_SCLK_DIV_B_S 14 923 /** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; 924 * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. 925 */ 926 #define LP_I2C_SCLK_SEL (BIT(20)) 927 #define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) 928 #define LP_I2C_SCLK_SEL_V 0x00000001U 929 #define LP_I2C_SCLK_SEL_S 20 930 /** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; 931 * The clock switch for i2c module 932 */ 933 #define LP_I2C_SCLK_ACTIVE (BIT(21)) 934 #define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) 935 #define LP_I2C_SCLK_ACTIVE_V 0x00000001U 936 #define LP_I2C_SCLK_ACTIVE_S 21 937 938 /** LP_I2C_COMD0_REG register 939 * I2C command register 0 940 */ 941 #define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) 942 /** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; 943 * This is the content of command 0. It consists of three parts: 944 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 945 * Byte_num represents the number of bytes that need to be sent or received. 946 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 947 * structure for more 948 * Information. 949 */ 950 #define LP_I2C_COMMAND0 0x00003FFFU 951 #define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) 952 #define LP_I2C_COMMAND0_V 0x00003FFFU 953 #define LP_I2C_COMMAND0_S 0 954 /** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; 955 * When command 0 is done in I2C Master mode, this bit changes to high 956 * level. 957 */ 958 #define LP_I2C_COMMAND0_DONE (BIT(31)) 959 #define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) 960 #define LP_I2C_COMMAND0_DONE_V 0x00000001U 961 #define LP_I2C_COMMAND0_DONE_S 31 962 963 /** LP_I2C_COMD1_REG register 964 * I2C command register 1 965 */ 966 #define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) 967 /** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; 968 * This is the content of command 1. It consists of three parts: 969 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 970 * Byte_num represents the number of bytes that need to be sent or received. 971 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 972 * structure for more 973 * Information. 974 */ 975 #define LP_I2C_COMMAND1 0x00003FFFU 976 #define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) 977 #define LP_I2C_COMMAND1_V 0x00003FFFU 978 #define LP_I2C_COMMAND1_S 0 979 /** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; 980 * When command 1 is done in I2C Master mode, this bit changes to high 981 * level. 982 */ 983 #define LP_I2C_COMMAND1_DONE (BIT(31)) 984 #define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) 985 #define LP_I2C_COMMAND1_DONE_V 0x00000001U 986 #define LP_I2C_COMMAND1_DONE_S 31 987 988 /** LP_I2C_COMD2_REG register 989 * I2C command register 2 990 */ 991 #define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) 992 /** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; 993 * This is the content of command 2. It consists of three parts: 994 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 995 * Byte_num represents the number of bytes that need to be sent or received. 996 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 997 * structure for more 998 * Information. 999 */ 1000 #define LP_I2C_COMMAND2 0x00003FFFU 1001 #define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) 1002 #define LP_I2C_COMMAND2_V 0x00003FFFU 1003 #define LP_I2C_COMMAND2_S 0 1004 /** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; 1005 * When command 2 is done in I2C Master mode, this bit changes to high 1006 * Level. 1007 */ 1008 #define LP_I2C_COMMAND2_DONE (BIT(31)) 1009 #define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) 1010 #define LP_I2C_COMMAND2_DONE_V 0x00000001U 1011 #define LP_I2C_COMMAND2_DONE_S 31 1012 1013 /** LP_I2C_COMD3_REG register 1014 * I2C command register 3 1015 */ 1016 #define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) 1017 /** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; 1018 * This is the content of command 3. It consists of three parts: 1019 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 1020 * Byte_num represents the number of bytes that need to be sent or received. 1021 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 1022 * structure for more 1023 * Information. 1024 */ 1025 #define LP_I2C_COMMAND3 0x00003FFFU 1026 #define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) 1027 #define LP_I2C_COMMAND3_V 0x00003FFFU 1028 #define LP_I2C_COMMAND3_S 0 1029 /** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; 1030 * When command 3 is done in I2C Master mode, this bit changes to high 1031 * level. 1032 */ 1033 #define LP_I2C_COMMAND3_DONE (BIT(31)) 1034 #define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) 1035 #define LP_I2C_COMMAND3_DONE_V 0x00000001U 1036 #define LP_I2C_COMMAND3_DONE_S 31 1037 1038 /** LP_I2C_COMD4_REG register 1039 * I2C command register 4 1040 */ 1041 #define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) 1042 /** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; 1043 * This is the content of command 4. It consists of three parts: 1044 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 1045 * Byte_num represents the number of bytes that need to be sent or received. 1046 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 1047 * structure for more 1048 * Information. 1049 */ 1050 #define LP_I2C_COMMAND4 0x00003FFFU 1051 #define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) 1052 #define LP_I2C_COMMAND4_V 0x00003FFFU 1053 #define LP_I2C_COMMAND4_S 0 1054 /** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; 1055 * When command 4 is done in I2C Master mode, this bit changes to high 1056 * level. 1057 */ 1058 #define LP_I2C_COMMAND4_DONE (BIT(31)) 1059 #define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) 1060 #define LP_I2C_COMMAND4_DONE_V 0x00000001U 1061 #define LP_I2C_COMMAND4_DONE_S 31 1062 1063 /** LP_I2C_COMD5_REG register 1064 * I2C command register 5 1065 */ 1066 #define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) 1067 /** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; 1068 * This is the content of command 5. It consists of three parts: 1069 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 1070 * Byte_num represents the number of bytes that need to be sent or received. 1071 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 1072 * structure for more 1073 * Information. 1074 */ 1075 #define LP_I2C_COMMAND5 0x00003FFFU 1076 #define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) 1077 #define LP_I2C_COMMAND5_V 0x00003FFFU 1078 #define LP_I2C_COMMAND5_S 0 1079 /** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; 1080 * When command 5 is done in I2C Master mode, this bit changes to high level. 1081 */ 1082 #define LP_I2C_COMMAND5_DONE (BIT(31)) 1083 #define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) 1084 #define LP_I2C_COMMAND5_DONE_V 0x00000001U 1085 #define LP_I2C_COMMAND5_DONE_S 31 1086 1087 /** LP_I2C_COMD6_REG register 1088 * I2C command register 6 1089 */ 1090 #define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) 1091 /** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; 1092 * This is the content of command 6. It consists of three parts: 1093 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 1094 * Byte_num represents the number of bytes that need to be sent or received. 1095 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 1096 * structure for more 1097 * Information. 1098 */ 1099 #define LP_I2C_COMMAND6 0x00003FFFU 1100 #define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) 1101 #define LP_I2C_COMMAND6_V 0x00003FFFU 1102 #define LP_I2C_COMMAND6_S 0 1103 /** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; 1104 * When command 6 is done in I2C Master mode, this bit changes to high level. 1105 */ 1106 #define LP_I2C_COMMAND6_DONE (BIT(31)) 1107 #define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) 1108 #define LP_I2C_COMMAND6_DONE_V 0x00000001U 1109 #define LP_I2C_COMMAND6_DONE_S 31 1110 1111 /** LP_I2C_COMD7_REG register 1112 * I2C command register 7 1113 */ 1114 #define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) 1115 /** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; 1116 * This is the content of command 7. It consists of three parts: 1117 * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. 1118 * Byte_num represents the number of bytes that need to be sent or received. 1119 * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd 1120 * structure for more 1121 * Information. 1122 */ 1123 #define LP_I2C_COMMAND7 0x00003FFFU 1124 #define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) 1125 #define LP_I2C_COMMAND7_V 0x00003FFFU 1126 #define LP_I2C_COMMAND7_S 0 1127 /** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; 1128 * When command 7 is done in I2C Master mode, this bit changes to high level. 1129 */ 1130 #define LP_I2C_COMMAND7_DONE (BIT(31)) 1131 #define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) 1132 #define LP_I2C_COMMAND7_DONE_V 0x00000001U 1133 #define LP_I2C_COMMAND7_DONE_S 31 1134 1135 /** LP_I2C_SCL_ST_TIME_OUT_REG register 1136 * SCL status time out register 1137 */ 1138 #define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) 1139 /** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; 1140 * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 1141 */ 1142 #define LP_I2C_SCL_ST_TO_I2C 0x0000001FU 1143 #define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) 1144 #define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU 1145 #define LP_I2C_SCL_ST_TO_LP_I2C_S 0 1146 1147 /** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register 1148 * SCL main status time out register 1149 */ 1150 #define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) 1151 /** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; 1152 * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more 1153 * than 23 1154 */ 1155 #define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU 1156 #define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) 1157 #define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU 1158 #define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 1159 1160 /** LP_I2C_SCL_SP_CONF_REG register 1161 * Power configuration register 1162 */ 1163 #define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) 1164 /** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; 1165 * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses 1166 * equals to reg_scl_rst_slv_num[4:0]. 1167 */ 1168 #define LP_I2C_SCL_RST_SLV_EN (BIT(0)) 1169 #define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) 1170 #define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U 1171 #define LP_I2C_SCL_RST_SLV_EN_S 0 1172 /** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; 1173 * Configure the pulses of SCL generated in I2C master mode. Valid when 1174 * reg_scl_rst_slv_en is 1. 1175 */ 1176 #define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU 1177 #define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) 1178 #define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU 1179 #define LP_I2C_SCL_RST_SLV_NUM_S 1 1180 /** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; 1181 * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power 1182 * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 1183 */ 1184 #define LP_I2C_SCL_PD_EN (BIT(6)) 1185 #define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) 1186 #define LP_I2C_SCL_PD_EN_V 0x00000001U 1187 #define LP_I2C_SCL_PD_EN_S 6 1188 /** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; 1189 * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power 1190 * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 1191 */ 1192 #define LP_I2C_SDA_PD_EN (BIT(7)) 1193 #define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) 1194 #define LP_I2C_SDA_PD_EN_V 0x00000001U 1195 #define LP_I2C_SDA_PD_EN_S 7 1196 1197 /** LP_I2C_DATE_REG register 1198 * Version register 1199 */ 1200 #define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) 1201 /** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 35656003; 1202 * This is the the version register. 1203 */ 1204 #define LP_I2C_DATE 0xFFFFFFFFU 1205 #define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) 1206 #define LP_I2C_DATE_V 0xFFFFFFFFU 1207 #define LP_I2C_DATE_S 0 1208 1209 /** LP_I2C_TXFIFO_START_ADDR_REG register 1210 * I2C TXFIFO base address register 1211 */ 1212 #define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) 1213 /** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; 1214 * This is the I2C txfifo first address. 1215 */ 1216 #define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU 1217 #define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) 1218 #define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU 1219 #define LP_I2C_TXFIFO_START_ADDR_S 0 1220 1221 /** LP_I2C_RXFIFO_START_ADDR_REG register 1222 * I2C RXFIFO base address register 1223 */ 1224 #define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) 1225 /** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; 1226 * This is the I2C rxfifo first address. 1227 */ 1228 #define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU 1229 #define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) 1230 #define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU 1231 #define LP_I2C_RXFIFO_START_ADDR_S 0 1232 1233 #ifdef __cplusplus 1234 } 1235 #endif 1236
