1 /*
2  * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice, this
11  *    list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  *    contributors may be used to endorse or promote products derived from this
19  *    software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef NRFX_INTERCONNECT_APB_HALTIUM_RADIOCORE_H__
35 #define NRFX_INTERCONNECT_APB_HALTIUM_RADIOCORE_H__
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 #if ((NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(020) | \
42      NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(020)) > \
43      NRFX_BIT_MASK(DPPI020_CH_NUM))
44 #error "Invalid mask for DPPIC020 subscibe/publish defined."
45 #endif
46 
47 #if ((NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(030) | \
48      NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(030)) > \
49      NRFX_BIT_MASK(DPPI030_CH_NUM))
50 #error "Invalid mask for DPPIC030 subscibe/publish defined."
51 #endif
52 
53 #ifndef NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE
54 #define NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE \
55 NRFX_DPPI_CHANNELS_ENTRY(020);                  \
56 NRFX_DPPI_CHANNELS_ENTRY(030);
57 #endif // NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE
58 
59 #define NRFX_INTERCONNECT_APB_LOCAL_BUSES_PROP                                                     \
60 {                                                                                                  \
61     NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(DPPIC020),                                              \
62                      (NRFX_INTERCONNECT_APB_PROP_ENTRY(020, NRF_PPIB020, 0x10000)), ()) /* APB2 */ \
63     NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(DPPIC030),                                              \
64                      (NRFX_INTERCONNECT_APB_PROP_ENTRY(030, NRF_PPIB030, 0x10000)), ()) /* APB3 */ \
65 }
66 
67 #ifdef __cplusplus
68 }
69 #endif
70 
71 #endif // NRFX_INTERCONNECT_APB_HALTIUM_RADIOCORE_H__
72