1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_CRYPTO_DMA_REG_H_ 15 #define _SOC_CRYPTO_DMA_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 23 /* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */ 24 /* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */ 25 /*description: */ 26 #define CONF0_REG_GEN_CLK_EN (BIT(13)) 27 #define CONF0_REG_GEN_CLK_EN_M (BIT(13)) 28 #define CONF0_REG_GEN_CLK_EN_V 0x1 29 #define CONF0_REG_GEN_CLK_EN_S 13 30 /* CONF0_REG_MEM_TRANS_EN: RW ;bitpos:[12] ;default: 1'b0 ; */ 31 /*description: */ 32 #define CONF0_REG_MEM_TRANS_EN (BIT(12)) 33 #define CONF0_REG_MEM_TRANS_EN_M (BIT(12)) 34 #define CONF0_REG_MEM_TRANS_EN_V 0x1 35 #define CONF0_REG_MEM_TRANS_EN_S 12 36 /* CONF0_REG_OUT_DATA_BURST_EN: RW ;bitpos:[11] ;default: 1'b0 ; */ 37 /*description: */ 38 #define CONF0_REG_OUT_DATA_BURST_EN (BIT(11)) 39 #define CONF0_REG_OUT_DATA_BURST_EN_M (BIT(11)) 40 #define CONF0_REG_OUT_DATA_BURST_EN_V 0x1 41 #define CONF0_REG_OUT_DATA_BURST_EN_S 11 42 /* CONF0_REG_INDSCR_BURST_EN: RW ;bitpos:[10] ;default: 1'b0 ; */ 43 /*description: */ 44 #define CONF0_REG_INDSCR_BURST_EN (BIT(10)) 45 #define CONF0_REG_INDSCR_BURST_EN_M (BIT(10)) 46 #define CONF0_REG_INDSCR_BURST_EN_V 0x1 47 #define CONF0_REG_INDSCR_BURST_EN_S 10 48 /* CONF0_REG_OUTDSCR_BURST_EN: RW ;bitpos:[9] ;default: 1'b0 ; */ 49 /*description: */ 50 #define CONF0_REG_OUTDSCR_BURST_EN (BIT(9)) 51 #define CONF0_REG_OUTDSCR_BURST_EN_M (BIT(9)) 52 #define CONF0_REG_OUTDSCR_BURST_EN_V 0x1 53 #define CONF0_REG_OUTDSCR_BURST_EN_S 9 54 /* CONF0_REG_OUT_EOF_MODE: RW ;bitpos:[8] ;default: 1'b0 ; */ 55 /*description: */ 56 #define CONF0_REG_OUT_EOF_MODE (BIT(8)) 57 #define CONF0_REG_OUT_EOF_MODE_M (BIT(8)) 58 #define CONF0_REG_OUT_EOF_MODE_V 0x1 59 #define CONF0_REG_OUT_EOF_MODE_S 8 60 /* CONF0_REG_OUT_NO_RESTART_CLR: RW ;bitpos:[7] ;default: 1'b0 ; */ 61 /*description: */ 62 #define CONF0_REG_OUT_NO_RESTART_CLR (BIT(7)) 63 #define CONF0_REG_OUT_NO_RESTART_CLR_M (BIT(7)) 64 #define CONF0_REG_OUT_NO_RESTART_CLR_V 0x1 65 #define CONF0_REG_OUT_NO_RESTART_CLR_S 7 66 /* CONF0_REG_OUT_AUTO_WRBACK: RW ;bitpos:[6] ;default: 1'b0 ; */ 67 /*description: */ 68 #define CONF0_REG_OUT_AUTO_WRBACK (BIT(6)) 69 #define CONF0_REG_OUT_AUTO_WRBACK_M (BIT(6)) 70 #define CONF0_REG_OUT_AUTO_WRBACK_V 0x1 71 #define CONF0_REG_OUT_AUTO_WRBACK_S 6 72 /* CONF0_REG_OUT_LOOP_TEST: RW ;bitpos:[5] ;default: 1'b0 ; */ 73 /*description: */ 74 #define CONF0_REG_OUT_LOOP_TEST (BIT(5)) 75 #define CONF0_REG_OUT_LOOP_TEST_M (BIT(5)) 76 #define CONF0_REG_OUT_LOOP_TEST_V 0x1 77 #define CONF0_REG_OUT_LOOP_TEST_S 5 78 /* CONF0_REG_IN_LOOP_TEST: RW ;bitpos:[4] ;default: 1'b0 ; */ 79 /*description: */ 80 #define CONF0_REG_IN_LOOP_TEST (BIT(4)) 81 #define CONF0_REG_IN_LOOP_TEST_M (BIT(4)) 82 #define CONF0_REG_IN_LOOP_TEST_V 0x1 83 #define CONF0_REG_IN_LOOP_TEST_S 4 84 /* CONF0_REG_AHBM_RST: RW ;bitpos:[3] ;default: 1'b0 ; */ 85 /*description: */ 86 #define CONF0_REG_AHBM_RST (BIT(3)) 87 #define CONF0_REG_AHBM_RST_M (BIT(3)) 88 #define CONF0_REG_AHBM_RST_V 0x1 89 #define CONF0_REG_AHBM_RST_S 3 90 /* CONF0_REG_AHBM_FIFO_RST: RW ;bitpos:[2] ;default: 1'b0 ; */ 91 /*description: */ 92 #define CONF0_REG_AHBM_FIFO_RST (BIT(2)) 93 #define CONF0_REG_AHBM_FIFO_RST_M (BIT(2)) 94 #define CONF0_REG_AHBM_FIFO_RST_V 0x1 95 #define CONF0_REG_AHBM_FIFO_RST_S 2 96 /* CONF0_REG_OUT_RST: RW ;bitpos:[1] ;default: 1'b0 ; */ 97 /*description: */ 98 #define CONF0_REG_OUT_RST (BIT(1)) 99 #define CONF0_REG_OUT_RST_M (BIT(1)) 100 #define CONF0_REG_OUT_RST_V 0x1 101 #define CONF0_REG_OUT_RST_S 1 102 /* CONF0_REG_IN_RST: RW ;bitpos:[0] ;default: 1'b0 ; */ 103 /*description: */ 104 #define CONF0_REG_IN_RST (BIT(0)) 105 #define CONF0_REG_IN_RST_M (BIT(0)) 106 #define CONF0_REG_IN_RST_V 0x1 107 #define CONF0_REG_IN_RST_S 0 108 /* CRYPTO_DMA_INT_RAW : RO ;bitpos:[31:10] ;default: 22'h0 ; */ 109 /* INT_RAW_OUT_TOTAL_EOF : RW ;bitpos:[8] ;default: 1'b0 ; */ 110 /*description: */ 111 #define INT_RAW_OUT_TOTAL_EOF ( BIT(8)) 112 #define INT_RAW_OUT_TOTAL_EOF_M (BIT(8)) 113 #define INT_RAW_OUT_TOTAL_EOF_V 0x1 114 #define INT_RAW_OUT_TOTAL_EOF_S 8 115 /* INT_RAW_IN_SUC_EOF : RW ;bitpos:[1] ;default: 1'b0 ; */ 116 /*description: */ 117 #define INT_RAW_IN_SUC_EOF ( BIT(1)) 118 #define INT_RAW_IN_SUC_EOF_M (BIT(1)) 119 #define INT_RAW_IN_SUC_EOF_V 0x1 120 #define INT_RAW_IN_SUC_EOF_S 1 121 /* CRYPTO_DMA_OUT_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */ 122 /* OUT_LINK_REG_OUTLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */ 123 /*description: */ 124 #define OUT_LINK_REG_OUTLINK_RESTART ( BIT(30)) 125 #define OUT_LINK_REG_OUTLINK_RESTART_M (BIT(30)) 126 #define OUT_LINK_REG_OUTLINK_RESTART_V 0x1 127 #define OUT_LINK_REG_OUTLINK_RESTART_S 30 128 /* OUT_LINK_REG_OUTLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */ 129 /*description: */ 130 #define OUT_LINK_REG_OUTLINK_START ( BIT(29)) 131 #define OUT_LINK_REG_OUTLINK_START_M (BIT(29)) 132 #define OUT_LINK_REG_OUTLINK_START_V 0x1 133 #define OUT_LINK_REG_OUTLINK_START_S 29 134 /* OUT_LINK_REG_OUTLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */ 135 /*description: */ 136 #define OUT_LINK_REG_OUTLINK_STOP ( BIT(28)) 137 #define OUT_LINK_REG_OUTLINK_STOP_M (BIT(28)) 138 #define OUT_LINK_REG_OUTLINK_STOP_V 0x1 139 #define OUT_LINK_REG_OUTLINK_STOP_S 28 140 /* OUT_LINK_REG_OUTLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */ 141 /*description: */ 142 #define OUT_LINK_REG_OUTLINK_ADDR 0x000FFFFF 143 #define OUT_LINK_REG_OUTLINK_ADDR_M (OUT_LINK_REG_OUTLINK_ADDR_V<<OUT_LINK_REG_OUTLINK_ADDR_S) 144 #define OUT_LINK_REG_OUTLINK_ADDR_V 0xFFFFF 145 #define OUT_LINK_REG_OUTLINK_ADDR_S 0 146 /* CRYPTO_DMA_IN_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */ 147 /* IN_LINK_REG_INLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */ 148 /*description: */ 149 #define IN_LINK_REG_INLINK_RESTART ( BIT(30)) 150 #define IN_LINK_REG_INLINK_RESTART_M (BIT(30)) 151 #define IN_LINK_REG_INLINK_RESTART_V 0x1 152 #define IN_LINK_REG_INLINK_RESTART_S 30 153 /* IN_LINK_REG_INLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */ 154 /*description: */ 155 #define IN_LINK_REG_INLINK_START ( BIT(29)) 156 #define IN_LINK_REG_INLINK_START_M (BIT(29)) 157 #define IN_LINK_REG_INLINK_START_V 0x1 158 #define IN_LINK_REG_INLINK_START_S 29 159 /* IN_LINK_REG_INLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */ 160 /*description: */ 161 #define IN_LINK_REG_INLINK_STOP ( BIT(28)) 162 #define IN_LINK_REG_INLINK_STOP_M (BIT(28)) 163 #define IN_LINK_REG_INLINK_STOP_V 0x1 164 #define IN_LINK_REG_INLINK_STOP_S 28 165 /* IN_LINK_REG_INLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */ 166 /*description: */ 167 #define IN_LINK_REG_INLINK_ADDR 0x000FFFFF 168 #define IN_LINK_REG_INLINK_ADDR_M (IN_LINK_REG_INLINK_ADDR_V<<IN_LINK_REG_INLINK_ADDR_S) 169 #define IN_LINK_REG_INLINK_ADDR_V 0xFFFFF 170 #define IN_LINK_REG_INLINK_ADDR_S 0 171 /* CRYPTO_DMA_AES_SHA_SELECT : RO ;bitpos:[31:1] ;default: 31'b0 ; */ 172 /* AES_SHA_SELECT : RW ;bitpos:[0] ;default: 1'b0 ; */ 173 /*description: */ 174 #define AES_SHA_SELECT ( BIT(0)) 175 #define AES_SHA_SELECT_M (BIT(0)) 176 #define AES_SHA_SELECT_V 0x1 177 #define AES_SHA_SELECT_S 0 178 179 #ifdef __cplusplus 180 } 181 #endif 182 183 184 185 #endif /*_SOC_CRYPTO_DMA_REG_H_ */ 186
