1 /** 2 * @file skbd_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SKBD_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SKBD_REVA_REGS_H_ 27 #define _SKBD_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup skbd_reva 65 * @defgroup skbd_reva_registers SKBD_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SKBD_REVA Peripheral Module. 67 * @details Secure Keyboard 68 */ 69 70 /** 71 * @ingroup skbd_reva_registers 72 * Structure type to access the SKBD_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> SKBD_REVA CTRL0 Register */ 76 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SKBD_REVA CTRL1 Register */ 77 __I uint32_t sr; /**< <tt>\b 0x08:</tt> SKBD_REVA SR Register */ 78 __IO uint32_t ier; /**< <tt>\b 0x0C:</tt> SKBD_REVA IER Register */ 79 __IO uint32_t isr; /**< <tt>\b 0x10:</tt> SKBD_REVA ISR Register */ 80 __I uint32_t evt[4]; /**< <tt>\b 0x14:</tt> SKBD_REVA EVT Register */ 81 } mxc_skbd_reva_regs_t; 82 83 /* Register offsets for module SKBD_REVA */ 84 /** 85 * @ingroup skbd_reva_registers 86 * @defgroup SKBD_REVA_Register_Offsets Register Offsets 87 * @brief SKBD_REVA Peripheral Register Offsets from the SKBD_REVA Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_SKBD_REVA_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from SKBD_REVA Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_SKBD_REVA_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SKBD_REVA Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_SKBD_REVA_SR ((uint32_t)0x00000008UL) /**< Offset from SKBD_REVA Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_SKBD_REVA_IER ((uint32_t)0x0000000CUL) /**< Offset from SKBD_REVA Base Address: <tt> 0x000C</tt> */ 94 #define MXC_R_SKBD_REVA_ISR ((uint32_t)0x00000010UL) /**< Offset from SKBD_REVA Base Address: <tt> 0x0010</tt> */ 95 #define MXC_R_SKBD_REVA_EVT ((uint32_t)0x00000014UL) /**< Offset from SKBD_REVA Base Address: <tt> 0x0014</tt> */ 96 /**@} end of group skbd_reva_registers */ 97 98 /** 99 * @ingroup skbd_reva_registers 100 * @defgroup SKBD_REVA_CTRL0 SKBD_REVA_CTRL0 101 * @brief Input Output Select Bits. Each bit of IOSEL selects the pin direction for the 102 * corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. 103 * @{ 104 */ 105 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_0_POS 0 /**< CTRL0_KBDIO_0 Position */ 106 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_0 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_0_POS)) /**< CTRL0_KBDIO_0 Mask */ 107 108 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_1_POS 1 /**< CTRL0_KBDIO_1 Position */ 109 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_1 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_1_POS)) /**< CTRL0_KBDIO_1 Mask */ 110 111 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_2_POS 2 /**< CTRL0_KBDIO_2 Position */ 112 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_2 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_2_POS)) /**< CTRL0_KBDIO_2 Mask */ 113 114 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_3_POS 3 /**< CTRL0_KBDIO_3 Position */ 115 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_3 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_3_POS)) /**< CTRL0_KBDIO_3 Mask */ 116 117 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_4_POS 4 /**< CTRL0_KBDIO_4 Position */ 118 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_4 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_4_POS)) /**< CTRL0_KBDIO_4 Mask */ 119 120 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_5_POS 5 /**< CTRL0_KBDIO_5 Position */ 121 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_5 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_5_POS)) /**< CTRL0_KBDIO_5 Mask */ 122 123 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_6_POS 6 /**< CTRL0_KBDIO_6 Position */ 124 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_6 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_6_POS)) /**< CTRL0_KBDIO_6 Mask */ 125 126 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_7_POS 7 /**< CTRL0_KBDIO_7 Position */ 127 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_7 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_7_POS)) /**< CTRL0_KBDIO_7 Mask */ 128 129 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_8_POS 8 /**< CTRL0_KBDIO_8 Position */ 130 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_8 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_8_POS)) /**< CTRL0_KBDIO_8 Mask */ 131 132 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_9_POS 9 /**< CTRL0_KBDIO_9 Position */ 133 #define MXC_F_SKBD_REVA_CTRL0_KBDIO_9 ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL0_KBDIO_9_POS)) /**< CTRL0_KBDIO_9 Mask */ 134 135 /**@} end of group SKBD_REVA_CTRL0_Register */ 136 137 /** 138 * @ingroup skbd_reva_registers 139 * @defgroup SKBD_REVA_CTRL1 SKBD_REVA_CTRL1 140 * @brief Control Register 1 141 * @{ 142 */ 143 #define MXC_F_SKBD_REVA_CTRL1_AUTOEN_POS 0 /**< CTRL1_AUTOEN Position */ 144 #define MXC_F_SKBD_REVA_CTRL1_AUTOEN ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL1_AUTOEN_POS)) /**< CTRL1_AUTOEN Mask */ 145 146 #define MXC_F_SKBD_REVA_CTRL1_CLEAR_POS 1 /**< CTRL1_CLEAR Position */ 147 #define MXC_F_SKBD_REVA_CTRL1_CLEAR ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_CTRL1_CLEAR_POS)) /**< CTRL1_CLEAR Mask */ 148 149 #define MXC_F_SKBD_REVA_CTRL1_OUTNB_POS 8 /**< CTRL1_OUTNB Position */ 150 #define MXC_F_SKBD_REVA_CTRL1_OUTNB ((uint32_t)(0x7UL << MXC_F_SKBD_REVA_CTRL1_OUTNB_POS)) /**< CTRL1_OUTNB Mask */ 151 152 #define MXC_F_SKBD_REVA_CTRL1_DBTM_POS 13 /**< CTRL1_DBTM Position */ 153 #define MXC_F_SKBD_REVA_CTRL1_DBTM ((uint32_t)(0x7UL << MXC_F_SKBD_REVA_CTRL1_DBTM_POS)) /**< CTRL1_DBTM Mask */ 154 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME4MS ((uint32_t)0x0UL) /**< CTRL1_DBTM_TIME4MS Value */ 155 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME4MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME4MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME4MS Setting */ 156 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME5MS ((uint32_t)0x1UL) /**< CTRL1_DBTM_TIME5MS Value */ 157 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME5MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME5MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME5MS Setting */ 158 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME6MS ((uint32_t)0x2UL) /**< CTRL1_DBTM_TIME6MS Value */ 159 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME6MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME6MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME6MS Setting */ 160 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME7MS ((uint32_t)0x3UL) /**< CTRL1_DBTM_TIME7MS Value */ 161 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME7MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME7MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME7MS Setting */ 162 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME8MS ((uint32_t)0x4UL) /**< CTRL1_DBTM_TIME8MS Value */ 163 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME8MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME8MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME8MS Setting */ 164 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME10MS ((uint32_t)0x5UL) /**< CTRL1_DBTM_TIME10MS Value */ 165 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME10MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME10MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME10MS Setting */ 166 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME11MS ((uint32_t)0x6UL) /**< CTRL1_DBTM_TIME11MS Value */ 167 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME11MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME11MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME11MS Setting */ 168 #define MXC_V_SKBD_REVA_CTRL1_DBTM_TIME12MS ((uint32_t)0x7UL) /**< CTRL1_DBTM_TIME12MS Value */ 169 #define MXC_S_SKBD_REVA_CTRL1_DBTM_TIME12MS (MXC_V_SKBD_REVA_CTRL1_DBTM_TIME12MS << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME12MS Setting */ 170 171 /**@} end of group SKBD_REVA_CTRL1_Register */ 172 173 /** 174 * @ingroup skbd_reva_registers 175 * @defgroup SKBD_REVA_SR SKBD_REVA_SR 176 * @brief Status Register 177 * @{ 178 */ 179 #define MXC_F_SKBD_REVA_SR_BUSY_POS 0 /**< SR_BUSY Position */ 180 #define MXC_F_SKBD_REVA_SR_BUSY ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_SR_BUSY_POS)) /**< SR_BUSY Mask */ 181 182 /**@} end of group SKBD_REVA_SR_Register */ 183 184 /** 185 * @ingroup skbd_reva_registers 186 * @defgroup SKBD_REVA_IER SKBD_REVA_IER 187 * @brief Interrupt Enable Register 188 * @{ 189 */ 190 #define MXC_F_SKBD_REVA_IER_PUSHIE_POS 0 /**< IER_PUSHIE Position */ 191 #define MXC_F_SKBD_REVA_IER_PUSHIE ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_IER_PUSHIE_POS)) /**< IER_PUSHIE Mask */ 192 193 #define MXC_F_SKBD_REVA_IER_RELEASEIE_POS 1 /**< IER_RELEASEIE Position */ 194 #define MXC_F_SKBD_REVA_IER_RELEASEIE ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_IER_RELEASEIE_POS)) /**< IER_RELEASEIE Mask */ 195 196 #define MXC_F_SKBD_REVA_IER_OVERIE_POS 2 /**< IER_OVERIE Position */ 197 #define MXC_F_SKBD_REVA_IER_OVERIE ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_IER_OVERIE_POS)) /**< IER_OVERIE Mask */ 198 199 /**@} end of group SKBD_REVA_IER_Register */ 200 201 /** 202 * @ingroup skbd_reva_registers 203 * @defgroup SKBD_REVA_ISR SKBD_REVA_ISR 204 * @brief Interrupt Status Register 205 * @{ 206 */ 207 #define MXC_F_SKBD_REVA_ISR_PUSHIS_POS 0 /**< ISR_PUSHIS Position */ 208 #define MXC_F_SKBD_REVA_ISR_PUSHIS ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_ISR_PUSHIS_POS)) /**< ISR_PUSHIS Mask */ 209 210 #define MXC_F_SKBD_REVA_ISR_RELEASEIS_POS 1 /**< ISR_RELEASEIS Position */ 211 #define MXC_F_SKBD_REVA_ISR_RELEASEIS ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_ISR_RELEASEIS_POS)) /**< ISR_RELEASEIS Mask */ 212 213 #define MXC_F_SKBD_REVA_ISR_OVERIS_POS 2 /**< ISR_OVERIS Position */ 214 #define MXC_F_SKBD_REVA_ISR_OVERIS ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_ISR_OVERIS_POS)) /**< ISR_OVERIS Mask */ 215 216 /**@} end of group SKBD_REVA_ISR_Register */ 217 218 /** 219 * @ingroup skbd_reva_registers 220 * @defgroup SKBD_REVA_EVT SKBD_REVA_EVT 221 * @brief Key Register 222 * @{ 223 */ 224 #define MXC_F_SKBD_REVA_EVT_IOIN_POS 0 /**< EVT_IOIN Position */ 225 #define MXC_F_SKBD_REVA_EVT_IOIN ((uint32_t)(0x7UL << MXC_F_SKBD_REVA_EVT_IOIN_POS)) /**< EVT_IOIN Mask */ 226 227 #define MXC_F_SKBD_REVA_EVT_IOOUT_POS 5 /**< EVT_IOOUT Position */ 228 #define MXC_F_SKBD_REVA_EVT_IOOUT ((uint32_t)(0x7UL << MXC_F_SKBD_REVA_EVT_IOOUT_POS)) /**< EVT_IOOUT Mask */ 229 230 #define MXC_F_SKBD_REVA_EVT_PUSH_POS 10 /**< EVT_PUSH Position */ 231 #define MXC_F_SKBD_REVA_EVT_PUSH ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_EVT_PUSH_POS)) /**< EVT_PUSH Mask */ 232 233 #define MXC_F_SKBD_REVA_EVT_READ_POS 11 /**< EVT_READ Position */ 234 #define MXC_F_SKBD_REVA_EVT_READ ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_EVT_READ_POS)) /**< EVT_READ Mask */ 235 236 #define MXC_F_SKBD_REVA_EVT_NEXT_POS 12 /**< EVT_NEXT Position */ 237 #define MXC_F_SKBD_REVA_EVT_NEXT ((uint32_t)(0x1UL << MXC_F_SKBD_REVA_EVT_NEXT_POS)) /**< EVT_NEXT Mask */ 238 239 /**@} end of group SKBD_REVA_EVT_Register */ 240 241 #ifdef __cplusplus 242 } 243 #endif 244 245 #endif /* _SKBD_REVA_REGS_H_ */ 246
