1 /**
2  * @file    simo_reva_regs.h
3  * @brief   Registers, Bit Masks and Bit Positions for the SIMO_REVA Peripheral Module.
4  */
5 
6 /******************************************************************************
7  *
8  * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9  * Analog Devices, Inc.),
10  * Copyright (C) 2023-2024 Analog Devices, Inc.
11  *
12  * Licensed under the Apache License, Version 2.0 (the "License");
13  * you may not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  *     http://www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an "AS IS" BASIS,
20  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  *
24  ******************************************************************************/
25 
26 #ifndef _SIMO_REVA_REGS_H_
27 #define _SIMO_REVA_REGS_H_
28 
29 /* **** Includes **** */
30 #include <stdint.h>
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #if defined (__ICCARM__)
37   #pragma system_include
38 #endif
39 
40 #if defined (__CC_ARM)
41   #pragma anon_unions
42 #endif
43 /// @cond
44 /*
45     If types are not defined elsewhere (CMSIS) define them here
46 */
47 #ifndef __IO
48 #define __IO volatile
49 #endif
50 #ifndef __I
51 #define __I  volatile const
52 #endif
53 #ifndef __O
54 #define __O  volatile
55 #endif
56 #ifndef __R
57 #define __R  volatile const
58 #endif
59 /// @endcond
60 
61 /* **** Definitions **** */
62 
63 /**
64  * @ingroup     simo_reva
65  * @defgroup    simo_reva_registers SIMO_REVA_Registers
66  * @brief       Registers, Bit Masks and Bit Positions for the SIMO_REVA Peripheral Module.
67  * @details Single Inductor Multiple Output Switching Converter
68  */
69 
70 /**
71  * @ingroup simo_reva_registers
72  * Structure type to access the SIMO_REVA Registers.
73  */
74 typedef struct {
75     __R  uint32_t rsv_0x0;
76     __IO uint32_t vrego_a;              /**< <tt>\b 0x0004:</tt> SIMO_REVA VREGO_A Register */
77     __IO uint32_t vrego_b;              /**< <tt>\b 0x0008:</tt> SIMO_REVA VREGO_B Register */
78     __IO uint32_t vrego_c;              /**< <tt>\b 0x000C:</tt> SIMO_REVA VREGO_C Register */
79     __IO uint32_t vrego_d;              /**< <tt>\b 0x0010:</tt> SIMO_REVA VREGO_D Register */
80     __IO uint32_t ipka;                 /**< <tt>\b 0x0014:</tt> SIMO_REVA IPKA Register */
81     __IO uint32_t ipkb;                 /**< <tt>\b 0x0018:</tt> SIMO_REVA IPKB Register */
82     __IO uint32_t maxton;               /**< <tt>\b 0x001C:</tt> SIMO_REVA MAXTON Register */
83     __I  uint32_t iload_a;              /**< <tt>\b 0x0020:</tt> SIMO_REVA ILOAD_A Register */
84     __I  uint32_t iload_b;              /**< <tt>\b 0x0024:</tt> SIMO_REVA ILOAD_B Register */
85     __I  uint32_t iload_c;              /**< <tt>\b 0x0028:</tt> SIMO_REVA ILOAD_C Register */
86     __I  uint32_t iload_d;              /**< <tt>\b 0x002C:</tt> SIMO_REVA ILOAD_D Register */
87     __IO uint32_t buck_alert_thr_a;     /**< <tt>\b 0x0030:</tt> SIMO_REVA BUCK_ALERT_THR_A Register */
88     __IO uint32_t buck_alert_thr_b;     /**< <tt>\b 0x0034:</tt> SIMO_REVA BUCK_ALERT_THR_B Register */
89     __IO uint32_t buck_alert_thr_c;     /**< <tt>\b 0x0038:</tt> SIMO_REVA BUCK_ALERT_THR_C Register */
90     __IO uint32_t buck_alert_thr_d;     /**< <tt>\b 0x003C:</tt> SIMO_REVA BUCK_ALERT_THR_D Register */
91     __I  uint32_t buck_out_ready;       /**< <tt>\b 0x0040:</tt> SIMO_REVA BUCK_OUT_READY Register */
92     __I  uint32_t zero_cross_cal_a;     /**< <tt>\b 0x0044:</tt> SIMO_REVA ZERO_CROSS_CAL_A Register */
93     __I  uint32_t zero_cross_cal_b;     /**< <tt>\b 0x0048:</tt> SIMO_REVA ZERO_CROSS_CAL_B Register */
94     __I  uint32_t zero_cross_cal_c;     /**< <tt>\b 0x004C:</tt> SIMO_REVA ZERO_CROSS_CAL_C Register */
95     __I  uint32_t zero_cross_cal_d;     /**< <tt>\b 0x0050:</tt> SIMO_REVA ZERO_CROSS_CAL_D Register */
96 } mxc_simo_reva_regs_t;
97 
98 /* Register offsets for module SIMO_REVA */
99 /**
100  * @ingroup    simo_reva_registers
101  * @defgroup   SIMO_REVA_Register_Offsets Register Offsets
102  * @brief      SIMO_REVA Peripheral Register Offsets from the SIMO_REVA Base Peripheral Address.
103  * @{
104  */
105  #define MXC_R_SIMO_REVA_VREGO_A            ((uint32_t)0x00000004UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0004</tt> */
106  #define MXC_R_SIMO_REVA_VREGO_B            ((uint32_t)0x00000008UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0008</tt> */
107  #define MXC_R_SIMO_REVA_VREGO_C            ((uint32_t)0x0000000CUL) /**< Offset from SIMO_REVA Base Address: <tt> 0x000C</tt> */
108  #define MXC_R_SIMO_REVA_VREGO_D            ((uint32_t)0x00000010UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0010</tt> */
109  #define MXC_R_SIMO_REVA_IPKA               ((uint32_t)0x00000014UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0014</tt> */
110  #define MXC_R_SIMO_REVA_IPKB               ((uint32_t)0x00000018UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0018</tt> */
111  #define MXC_R_SIMO_REVA_MAXTON             ((uint32_t)0x0000001CUL) /**< Offset from SIMO_REVA Base Address: <tt> 0x001C</tt> */
112  #define MXC_R_SIMO_REVA_ILOAD_A            ((uint32_t)0x00000020UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0020</tt> */
113  #define MXC_R_SIMO_REVA_ILOAD_B            ((uint32_t)0x00000024UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0024</tt> */
114  #define MXC_R_SIMO_REVA_ILOAD_C            ((uint32_t)0x00000028UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0028</tt> */
115  #define MXC_R_SIMO_REVA_ILOAD_D            ((uint32_t)0x0000002CUL) /**< Offset from SIMO_REVA Base Address: <tt> 0x002C</tt> */
116  #define MXC_R_SIMO_REVA_BUCK_ALERT_THR_A   ((uint32_t)0x00000030UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0030</tt> */
117  #define MXC_R_SIMO_REVA_BUCK_ALERT_THR_B   ((uint32_t)0x00000034UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0034</tt> */
118  #define MXC_R_SIMO_REVA_BUCK_ALERT_THR_C   ((uint32_t)0x00000038UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0038</tt> */
119  #define MXC_R_SIMO_REVA_BUCK_ALERT_THR_D   ((uint32_t)0x0000003CUL) /**< Offset from SIMO_REVA Base Address: <tt> 0x003C</tt> */
120  #define MXC_R_SIMO_REVA_BUCK_OUT_READY     ((uint32_t)0x00000040UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0040</tt> */
121  #define MXC_R_SIMO_REVA_ZERO_CROSS_CAL_A   ((uint32_t)0x00000044UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0044</tt> */
122  #define MXC_R_SIMO_REVA_ZERO_CROSS_CAL_B   ((uint32_t)0x00000048UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0048</tt> */
123  #define MXC_R_SIMO_REVA_ZERO_CROSS_CAL_C   ((uint32_t)0x0000004CUL) /**< Offset from SIMO_REVA Base Address: <tt> 0x004C</tt> */
124  #define MXC_R_SIMO_REVA_ZERO_CROSS_CAL_D   ((uint32_t)0x00000050UL) /**< Offset from SIMO_REVA Base Address: <tt> 0x0050</tt> */
125 /**@} end of group simo_reva_registers */
126 
127 /**
128  * @ingroup  simo_reva_registers
129  * @defgroup SIMO_REVA_VREGO_A SIMO_REVA_VREGO_A
130  * @brief    Buck Voltage Regulator A Control Register
131  * @{
132  */
133  #define MXC_F_SIMO_REVA_VREGO_A_VSETA_POS              0 /**< VREGO_A_VSETA Position */
134  #define MXC_F_SIMO_REVA_VREGO_A_VSETA                  ((uint32_t)(0x7FUL << MXC_F_SIMO_REVA_VREGO_A_VSETA_POS)) /**< VREGO_A_VSETA Mask */
135 
136  #define MXC_F_SIMO_REVA_VREGO_A_RANGEA_POS             7 /**< VREGO_A_RANGEA Position */
137  #define MXC_F_SIMO_REVA_VREGO_A_RANGEA                 ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_VREGO_A_RANGEA_POS)) /**< VREGO_A_RANGEA Mask */
138 
139 /**@} end of group SIMO_REVA_VREGO_A_Register */
140 
141 /**
142  * @ingroup  simo_reva_registers
143  * @defgroup SIMO_REVA_VREGO_B SIMO_REVA_VREGO_B
144  * @brief    Buck Voltage Regulator B Control Register
145  * @{
146  */
147  #define MXC_F_SIMO_REVA_VREGO_B_VSETB_POS              0 /**< VREGO_B_VSETB Position */
148  #define MXC_F_SIMO_REVA_VREGO_B_VSETB                  ((uint32_t)(0x7FUL << MXC_F_SIMO_REVA_VREGO_B_VSETB_POS)) /**< VREGO_B_VSETB Mask */
149 
150  #define MXC_F_SIMO_REVA_VREGO_B_RANGEB_POS             7 /**< VREGO_B_RANGEB Position */
151  #define MXC_F_SIMO_REVA_VREGO_B_RANGEB                 ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_VREGO_B_RANGEB_POS)) /**< VREGO_B_RANGEB Mask */
152 
153 /**@} end of group SIMO_REVA_VREGO_B_Register */
154 
155 /**
156  * @ingroup  simo_reva_registers
157  * @defgroup SIMO_REVA_VREGO_C SIMO_REVA_VREGO_C
158  * @brief    Buck Voltage Regulator C Control Register
159  * @{
160  */
161  #define MXC_F_SIMO_REVA_VREGO_C_VSETC_POS              0 /**< VREGO_C_VSETC Position */
162  #define MXC_F_SIMO_REVA_VREGO_C_VSETC                  ((uint32_t)(0x7FUL << MXC_F_SIMO_REVA_VREGO_C_VSETC_POS)) /**< VREGO_C_VSETC Mask */
163 
164  #define MXC_F_SIMO_REVA_VREGO_C_RANGEC_POS             7 /**< VREGO_C_RANGEC Position */
165  #define MXC_F_SIMO_REVA_VREGO_C_RANGEC                 ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_VREGO_C_RANGEC_POS)) /**< VREGO_C_RANGEC Mask */
166 
167 /**@} end of group SIMO_REVA_VREGO_C_Register */
168 
169 /**
170  * @ingroup  simo_reva_registers
171  * @defgroup SIMO_REVA_VREGO_D SIMO_REVA_VREGO_D
172  * @brief    Buck Voltage Regulator D Control Register
173  * @{
174  */
175  #define MXC_F_SIMO_REVA_VREGO_D_VSETD_POS              0 /**< VREGO_D_VSETD Position */
176  #define MXC_F_SIMO_REVA_VREGO_D_VSETD                  ((uint32_t)(0x7FUL << MXC_F_SIMO_REVA_VREGO_D_VSETD_POS)) /**< VREGO_D_VSETD Mask */
177 
178  #define MXC_F_SIMO_REVA_VREGO_D_RANGED_POS             7 /**< VREGO_D_RANGED Position */
179  #define MXC_F_SIMO_REVA_VREGO_D_RANGED                 ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_VREGO_D_RANGED_POS)) /**< VREGO_D_RANGED Mask */
180 
181 /**@} end of group SIMO_REVA_VREGO_D_Register */
182 
183 /**
184  * @ingroup  simo_reva_registers
185  * @defgroup SIMO_REVA_IPKA SIMO_REVA_IPKA
186  * @brief    High Side FET Peak Current VREGO_A/VREGO_B Register
187  * @{
188  */
189  #define MXC_F_SIMO_REVA_IPKA_IPKSETA_POS               0 /**< IPKA_IPKSETA Position */
190  #define MXC_F_SIMO_REVA_IPKA_IPKSETA                   ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_IPKA_IPKSETA_POS)) /**< IPKA_IPKSETA Mask */
191 
192  #define MXC_F_SIMO_REVA_IPKA_IPKSETB_POS               4 /**< IPKA_IPKSETB Position */
193  #define MXC_F_SIMO_REVA_IPKA_IPKSETB                   ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_IPKA_IPKSETB_POS)) /**< IPKA_IPKSETB Mask */
194 
195 /**@} end of group SIMO_REVA_IPKA_Register */
196 
197 /**
198  * @ingroup  simo_reva_registers
199  * @defgroup SIMO_REVA_IPKB SIMO_REVA_IPKB
200  * @brief    High Side FET Peak Current VREGO_C/VREGO_D Register
201  * @{
202  */
203  #define MXC_F_SIMO_REVA_IPKB_IPKSETC_POS               0 /**< IPKB_IPKSETC Position */
204  #define MXC_F_SIMO_REVA_IPKB_IPKSETC                   ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_IPKB_IPKSETC_POS)) /**< IPKB_IPKSETC Mask */
205 
206  #define MXC_F_SIMO_REVA_IPKB_IPKSETD_POS               4 /**< IPKB_IPKSETD Position */
207  #define MXC_F_SIMO_REVA_IPKB_IPKSETD                   ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_IPKB_IPKSETD_POS)) /**< IPKB_IPKSETD Mask */
208 
209 /**@} end of group SIMO_REVA_IPKB_Register */
210 
211 /**
212  * @ingroup  simo_reva_registers
213  * @defgroup SIMO_REVA_MAXTON SIMO_REVA_MAXTON
214  * @brief    Maximum High Side FET Time On Register
215  * @{
216  */
217  #define MXC_F_SIMO_REVA_MAXTON_TONSET_POS              0 /**< MAXTON_TONSET Position */
218  #define MXC_F_SIMO_REVA_MAXTON_TONSET                  ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_MAXTON_TONSET_POS)) /**< MAXTON_TONSET Mask */
219 
220 /**@} end of group SIMO_REVA_MAXTON_Register */
221 
222 /**
223  * @ingroup  simo_reva_registers
224  * @defgroup SIMO_REVA_ILOAD_A SIMO_REVA_ILOAD_A
225  * @brief    Buck Cycle Count VREGO_A Register
226  * @{
227  */
228  #define MXC_F_SIMO_REVA_ILOAD_A_ILOADA_POS             0 /**< ILOAD_A_ILOADA Position */
229  #define MXC_F_SIMO_REVA_ILOAD_A_ILOADA                 ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_ILOAD_A_ILOADA_POS)) /**< ILOAD_A_ILOADA Mask */
230 
231 /**@} end of group SIMO_REVA_ILOAD_A_Register */
232 
233 /**
234  * @ingroup  simo_reva_registers
235  * @defgroup SIMO_REVA_ILOAD_B SIMO_REVA_ILOAD_B
236  * @brief    Buck Cycle Count VREGO_B Register
237  * @{
238  */
239  #define MXC_F_SIMO_REVA_ILOAD_B_ILOADB_POS             0 /**< ILOAD_B_ILOADB Position */
240  #define MXC_F_SIMO_REVA_ILOAD_B_ILOADB                 ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_ILOAD_B_ILOADB_POS)) /**< ILOAD_B_ILOADB Mask */
241 
242 /**@} end of group SIMO_REVA_ILOAD_B_Register */
243 
244 /**
245  * @ingroup  simo_reva_registers
246  * @defgroup SIMO_REVA_ILOAD_C SIMO_REVA_ILOAD_C
247  * @brief    Buck Cycle Count VREGO_C Register
248  * @{
249  */
250  #define MXC_F_SIMO_REVA_ILOAD_C_ILOADC_POS             0 /**< ILOAD_C_ILOADC Position */
251  #define MXC_F_SIMO_REVA_ILOAD_C_ILOADC                 ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_ILOAD_C_ILOADC_POS)) /**< ILOAD_C_ILOADC Mask */
252 
253 /**@} end of group SIMO_REVA_ILOAD_C_Register */
254 
255 /**
256  * @ingroup  simo_reva_registers
257  * @defgroup SIMO_REVA_ILOAD_D SIMO_REVA_ILOAD_D
258  * @brief    Buck Cycle Count VREGO_D Register
259  * @{
260  */
261  #define MXC_F_SIMO_REVA_ILOAD_D_ILOADD_POS             0 /**< ILOAD_D_ILOADD Position */
262  #define MXC_F_SIMO_REVA_ILOAD_D_ILOADD                 ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_ILOAD_D_ILOADD_POS)) /**< ILOAD_D_ILOADD Mask */
263 
264 /**@} end of group SIMO_REVA_ILOAD_D_Register */
265 
266 /**
267  * @ingroup  simo_reva_registers
268  * @defgroup SIMO_REVA_BUCK_ALERT_THR_A SIMO_REVA_BUCK_ALERT_THR_A
269  * @brief    Buck Cycle Count Alert VERGO_A Register
270  * @{
271  */
272  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_A_BUCKTHRA_POS  0 /**< BUCK_ALERT_THR_A_BUCKTHRA Position */
273  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_A_BUCKTHRA      ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_BUCK_ALERT_THR_A_BUCKTHRA_POS)) /**< BUCK_ALERT_THR_A_BUCKTHRA Mask */
274 
275 /**@} end of group SIMO_REVA_BUCK_ALERT_THR_A_Register */
276 
277 /**
278  * @ingroup  simo_reva_registers
279  * @defgroup SIMO_REVA_BUCK_ALERT_THR_B SIMO_REVA_BUCK_ALERT_THR_B
280  * @brief    Buck Cycle Count Alert VERGO_B Register
281  * @{
282  */
283  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_B_BUCKTHRB_POS  0 /**< BUCK_ALERT_THR_B_BUCKTHRB Position */
284  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_B_BUCKTHRB      ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_BUCK_ALERT_THR_B_BUCKTHRB_POS)) /**< BUCK_ALERT_THR_B_BUCKTHRB Mask */
285 
286 /**@} end of group SIMO_REVA_BUCK_ALERT_THR_B_Register */
287 
288 /**
289  * @ingroup  simo_reva_registers
290  * @defgroup SIMO_REVA_BUCK_ALERT_THR_C SIMO_REVA_BUCK_ALERT_THR_C
291  * @brief    Buck Cycle Count Alert VERGO_C Register
292  * @{
293  */
294  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_C_BUCKTHRC_POS  0 /**< BUCK_ALERT_THR_C_BUCKTHRC Position */
295  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_C_BUCKTHRC      ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_BUCK_ALERT_THR_C_BUCKTHRC_POS)) /**< BUCK_ALERT_THR_C_BUCKTHRC Mask */
296 
297 /**@} end of group SIMO_REVA_BUCK_ALERT_THR_C_Register */
298 
299 /**
300  * @ingroup  simo_reva_registers
301  * @defgroup SIMO_REVA_BUCK_ALERT_THR_D SIMO_REVA_BUCK_ALERT_THR_D
302  * @brief    Buck Cycle Count Alert VERGO_D Register
303  * @{
304  */
305  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_D_BUCKTHRD_POS  0 /**< BUCK_ALERT_THR_D_BUCKTHRD Position */
306  #define MXC_F_SIMO_REVA_BUCK_ALERT_THR_D_BUCKTHRD      ((uint32_t)(0xFFUL << MXC_F_SIMO_REVA_BUCK_ALERT_THR_D_BUCKTHRD_POS)) /**< BUCK_ALERT_THR_D_BUCKTHRD Mask */
307 
308 /**@} end of group SIMO_REVA_BUCK_ALERT_THR_D_Register */
309 
310 /**
311  * @ingroup  simo_reva_registers
312  * @defgroup SIMO_REVA_BUCK_OUT_READY SIMO_REVA_BUCK_OUT_READY
313  * @brief    Buck Regulator Output Ready Register
314  * @{
315  */
316  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYA_POS 0 /**< BUCK_OUT_READY_BUCKOUTRDYA Position */
317  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYA     ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYA_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYA Mask */
318 
319  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYB_POS 1 /**< BUCK_OUT_READY_BUCKOUTRDYB Position */
320  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYB     ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYB_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYB Mask */
321 
322  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYC_POS 2 /**< BUCK_OUT_READY_BUCKOUTRDYC Position */
323  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYC     ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYC_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYC Mask */
324 
325  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYD_POS 3 /**< BUCK_OUT_READY_BUCKOUTRDYD Position */
326  #define MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYD     ((uint32_t)(0x1UL << MXC_F_SIMO_REVA_BUCK_OUT_READY_BUCKOUTRDYD_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYD Mask */
327 
328 /**@} end of group SIMO_REVA_BUCK_OUT_READY_Register */
329 
330 /**
331  * @ingroup  simo_reva_registers
332  * @defgroup SIMO_REVA_ZERO_CROSS_CAL_A SIMO_REVA_ZERO_CROSS_CAL_A
333  * @brief    Zero Cross Calibration VERGO_A Register
334  * @{
335  */
336  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_A_ZXCALA_POS    0 /**< ZERO_CROSS_CAL_A_ZXCALA Position */
337  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_A_ZXCALA        ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_ZERO_CROSS_CAL_A_ZXCALA_POS)) /**< ZERO_CROSS_CAL_A_ZXCALA Mask */
338 
339 /**@} end of group SIMO_REVA_ZERO_CROSS_CAL_A_Register */
340 
341 /**
342  * @ingroup  simo_reva_registers
343  * @defgroup SIMO_REVA_ZERO_CROSS_CAL_B SIMO_REVA_ZERO_CROSS_CAL_B
344  * @brief    Zero Cross Calibration VERGO_B Register
345  * @{
346  */
347  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_B_ZXCALB_POS    0 /**< ZERO_CROSS_CAL_B_ZXCALB Position */
348  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_B_ZXCALB        ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_ZERO_CROSS_CAL_B_ZXCALB_POS)) /**< ZERO_CROSS_CAL_B_ZXCALB Mask */
349 
350 /**@} end of group SIMO_REVA_ZERO_CROSS_CAL_B_Register */
351 
352 /**
353  * @ingroup  simo_reva_registers
354  * @defgroup SIMO_REVA_ZERO_CROSS_CAL_C SIMO_REVA_ZERO_CROSS_CAL_C
355  * @brief    Zero Cross Calibration VERGO_C Register
356  * @{
357  */
358  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_C_ZXCALC_POS    0 /**< ZERO_CROSS_CAL_C_ZXCALC Position */
359  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_C_ZXCALC        ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_ZERO_CROSS_CAL_C_ZXCALC_POS)) /**< ZERO_CROSS_CAL_C_ZXCALC Mask */
360 
361 /**@} end of group SIMO_REVA_ZERO_CROSS_CAL_C_Register */
362 
363 /**
364  * @ingroup  simo_reva_registers
365  * @defgroup SIMO_REVA_ZERO_CROSS_CAL_D SIMO_REVA_ZERO_CROSS_CAL_D
366  * @brief    Zero Cross Calibration VERGO_D Register
367  * @{
368  */
369  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_D_ZXCALD_POS    0 /**< ZERO_CROSS_CAL_D_ZXCALD Position */
370  #define MXC_F_SIMO_REVA_ZERO_CROSS_CAL_D_ZXCALD        ((uint32_t)(0xFUL << MXC_F_SIMO_REVA_ZERO_CROSS_CAL_D_ZXCALD_POS)) /**< ZERO_CROSS_CAL_D_ZXCALD Mask */
371 
372 /**@} end of group SIMO_REVA_ZERO_CROSS_CAL_D_Register */
373 
374 #ifdef __cplusplus
375 }
376 #endif
377 
378 #endif /* _SIMO_REVA_REGS_H_ */
379