1/*
2 * Copyright (c) 2024 Yishai Jaffe
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <dt-bindings/adc/adc.h>
11#include <dt-bindings/clock/silabs/xg23-clock.h>
12#include <freq.h>
13
14/ {
15	chosen {
16		zephyr,flash-controller = &msc;
17		zephyr,entropy = &se;
18	};
19
20	clocks {
21		hfxort: hfxort {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&hfxo>;
25		};
26		hfrcodpllrt: hfrcodpllrt {
27			#clock-cells = <0>;
28			compatible = "fixed-factor-clock";
29			clocks = <&hfrcodpll>;
30		};
31		sysclk: sysclk {
32			#clock-cells = <0>;
33			compatible = "fixed-factor-clock";
34			clocks = <&hfrcodpll>;
35		};
36		hclk: hclk {
37			#clock-cells = <0>;
38			compatible = "fixed-factor-clock";
39			clocks = <&sysclk>;
40			/* Divider 1, 2, 4, 8, or 16 */
41			clock-div = <1>;
42		};
43		pclk: pclk {
44			#clock-cells = <0>;
45			compatible = "fixed-factor-clock";
46			clocks = <&hclk>;
47			/* Divider 1 or 2 */
48			clock-div = <2>;
49		};
50		lspclk: lspclk {
51			#clock-cells = <0>;
52			compatible = "fixed-factor-clock";
53			clocks = <&pclk>;
54			/* Fixed divider of 2 */
55			clock-div = <2>;
56		};
57		hclkdiv1024: hclkdiv1024 {
58			#clock-cells = <0>;
59			compatible = "fixed-factor-clock";
60			clocks = <&hclk>;
61			/* Fixed divider of 1024 */
62			clock-div = <1024>;
63		};
64		traceclk: traceclk {
65			#clock-cells = <0>;
66			compatible = "fixed-factor-clock";
67			clocks = <&sysclk>;
68			/* Divider 1, 2 or 4 */
69			clock-div = <1>;
70		};
71		em01grpaclk: em01grpaclk {
72			#clock-cells = <0>;
73			compatible = "fixed-factor-clock";
74			clocks = <&hfrcodpll>;
75		};
76		em01grpcclk: em01grpcclk {
77			#clock-cells = <0>;
78			compatible = "fixed-factor-clock";
79			clocks = <&hfrcodpll>;
80		};
81		iadcclk: iadcclk {
82			#clock-cells = <0>;
83			compatible = "fixed-factor-clock";
84			clocks = <&em01grpaclk>;
85		};
86		lesensehfclk: lesensehfclk {
87			#clock-cells = <0>;
88			compatible = "fixed-factor-clock";
89			clocks = <&fsrco>;
90		};
91		em23grpaclk: em23grpaclk {
92			#clock-cells = <0>;
93			compatible = "fixed-factor-clock";
94			clocks = <&lfrco>;
95		};
96		em4grpaclk: em4grpaclk {
97			#clock-cells = <0>;
98			compatible = "fixed-factor-clock";
99			clocks = <&lfrco>;
100		};
101		sysrtcclk: sysrtcclk {
102			#clock-cells = <0>;
103			compatible = "fixed-factor-clock";
104			clocks = <&lfrco>;
105		};
106		wdog0clk: wdog0clk {
107			#clock-cells = <0>;
108			compatible = "fixed-factor-clock";
109			clocks = <&lfrco>;
110		};
111		wdog1clk: wdog1clk {
112			#clock-cells = <0>;
113			compatible = "fixed-factor-clock";
114			clocks = <&lfrco>;
115		};
116		lcdclk: lcdclk {
117			#clock-cells = <0>;
118			compatible = "fixed-factor-clock";
119			clocks = <&lfrco>;
120		};
121		pcnt0clk: pcnt0clk {
122			#clock-cells = <0>;
123			compatible = "fixed-factor-clock";
124			clocks = <&em23grpaclk>;
125		};
126		eusart0clk: eusart0clk {
127			#clock-cells = <0>;
128			compatible = "fixed-factor-clock";
129			clocks = <&em01grpcclk>;
130		};
131		systickclk: systickclk {
132			#clock-cells = <0>;
133			compatible = "fixed-factor-clock";
134			clocks = <&hclk>;
135		};
136		vdac0clk: vdac0clk {
137			#clock-cells = <0>;
138			compatible = "fixed-factor-clock";
139			clocks = <&em01grpaclk>;
140		};
141	};
142
143	cpus {
144		#address-cells = <1>;
145		#size-cells = <0>;
146
147		cpu0: cpu@0 {
148			device_type = "cpu";
149			compatible = "arm,cortex-m33";
150			reg = <0>;
151			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
152		};
153
154		power-states {
155			/*
156			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
157			 * enabled.
158			 */
159			pstate_em1: em1 {
160				compatible = "zephyr,power-state";
161				power-state-name = "runtime-idle";
162				min-residency-us = <4>;
163				/* HFXO remains active */
164				exit-latency-us = <2>;
165			};
166
167			/*
168			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
169			 * scaled down, etc.
170			 */
171			pstate_em2: em2 {
172				compatible = "zephyr,power-state";
173				power-state-name = "suspend-to-idle";
174				min-residency-us = <260>;
175				exit-latency-us = <250>;
176			};
177
178			/*
179			 * EM3 seems to be exactly the same as EM2 except that
180			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
181			 * as BURTC clock for the system to not lose track of time and
182			 * wake up.
183			 */
184			pstate_em3: em3 {
185				compatible = "zephyr,power-state";
186				power-state-name = "standby";
187				min-residency-us = <20000>;
188				exit-latency-us = <2000>;
189			};
190		};
191	};
192
193	sram0: memory@20000000 {
194		device_type = "memory";
195		compatible = "mmio-sram";
196	};
197
198	soc {
199		cmu: clock@50008000 {
200			compatible = "silabs,series-clock";
201			reg = <0x50008000 0x4000>;
202			interrupts = <48 0>;
203			interrupt-names = "cmu";
204			status = "okay";
205			#clock-cells = <2>;
206		};
207
208		fsrco: fsrco@50018000 {
209			#clock-cells = <0>;
210			compatible = "fixed-clock";
211			reg = <0x50018000 0x4000>;
212			clock-frequency = <DT_FREQ_M(20)>;
213		};
214
215		clk_hfxo: hfxo: hfxo@5a004000 {
216			#clock-cells = <0>;
217			compatible = "silabs,hfxo";
218			reg = <0x5a004000 0x4000>;
219			interrupts = <45 0>;
220			interrupt-names = "hfxo";
221			clock-frequency = <DT_FREQ_M(39)>;
222			ctune = <140>;
223			precision = <50>;
224			status = "disabled";
225		};
226
227		lfxo: lfxo@50020000 {
228			#clock-cells = <0>;
229			compatible = "silabs,series2-lfxo";
230			reg = <0x50020000 0x4000>;
231			clock-frequency = <32768>;
232			ctune = <63>;
233			precision = <50>;
234			timeout = <4096>;
235			status = "disabled";
236		};
237
238		hfrcodpll: hfrcodpll@50010000 {
239			#clock-cells = <0>;
240			compatible = "silabs,series2-hfrcodpll";
241			reg = <0x50010000 0x4000>;
242			clock-frequency = <DT_FREQ_M(19)>;
243		};
244
245		hfrcoem23: hfrcoem23@5a000000 {
246			#clock-cells = <0>;
247			compatible = "silabs,series2-hfrcoem23";
248			reg = <0x5a000000 0x4000>;
249			clock-frequency = <DT_FREQ_M(19)>;
250		};
251
252		lfrco: lfrco@50024000 {
253			#clock-cells = <0>;
254			compatible = "silabs,series2-lfrco";
255			reg = <0x50024000 0x4000>;
256			clock-frequency = <32768>;
257		};
258
259		ulfrco: ulfrco@50028000 {
260			#clock-cells = <0>;
261			compatible = "fixed-clock";
262			reg = <0x50028000 0x4000>;
263			clock-frequency = <1000>;
264		};
265
266		clkin0: clkin0@5003c49c {
267			#clock-cells = <0>;
268			compatible = "fixed-clock";
269			reg = <0x5003c49c 0x4>;
270			clock-frequency = <DT_FREQ_M(38)>;
271		};
272
273		msc: flash-controller@50030000 {
274			compatible = "silabs,gecko-flash-controller";
275			reg = <0x50030000 0x4000>;
276			interrupts = <51 0>;
277
278			#address-cells = <1>;
279			#size-cells = <1>;
280
281			flash0: flash@8000000 {
282				compatible = "soc-nv-flash";
283				write-block-size = <4>;
284				erase-block-size = <8192>;
285			};
286		};
287
288		usart0: usart@5005c000 {
289			compatible = "silabs,gecko-usart";
290			reg = <0x5005C000 0x4000>;
291			interrupts = <9 0>, <10 0>;
292			interrupt-names = "rx", "tx";
293			peripheral-id = <0>;
294			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
295			status = "disabled";
296		};
297
298		eusart0: eusart@5b010000 {
299			compatible = "silabs,gecko-spi-eusart";
300			reg = <0x5B010000 0x4000>;
301			interrupts = <11 0>, <12 0>;
302			interrupt-names = "rx", "tx";
303			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
304			status = "disabled";
305		};
306
307		eusart1: eusart@500a0000 {
308			compatible = "silabs,gecko-spi-eusart";
309			reg = <0x500A0000 0x4000>;
310			interrupts = <13 0>, <14 0>;
311			interrupt-names = "rx", "tx";
312			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
313			status = "disabled";
314		};
315
316		eusart2: eusart@500a4000 {
317			compatible = "silabs,gecko-spi-eusart";
318			reg = <0x500A4000 0x4000>;
319			interrupts = <15 0>, <16 0>;
320			interrupt-names = "rx", "tx";
321			clocks = <&cmu CLOCK_EUSART2 CLOCK_BRANCH_EM01GRPCCLK>;
322			status = "disabled";
323		};
324
325		burtc0: burtc@50064000 {
326			compatible = "silabs,gecko-burtc";
327			reg = <0x50064000 0x4000>;
328			interrupts = <18 0>;
329			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
330			status = "disabled";
331		};
332
333		se: semailbox@5c000000 {
334			compatible = "silabs,gecko-semailbox";
335			reg = <0x5c000000 0x80>;
336			interrupts = <66 3>, <67 3>, <68 3>;
337			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
338			status = "disabled";
339		};
340
341		i2c0: i2c@5b000000 {
342			compatible = "silabs,gecko-i2c";
343			clock-frequency = <I2C_BITRATE_STANDARD>;
344			#address-cells = <1>;
345			#size-cells = <0>;
346			reg = <0x5b000000 0x4000>;
347			interrupts = <28 0>;
348			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
349			status = "disabled";
350		};
351
352		i2c1: i2c@50068000 {
353			compatible = "silabs,gecko-i2c";
354			clock-frequency = <I2C_BITRATE_STANDARD>;
355			#address-cells = <1>;
356			#size-cells = <0>;
357			reg = <0x50068000 0x4000>;
358			interrupts = <29 0>;
359			clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
360			status = "disabled";
361		};
362
363		sysrtc0: stimer0: sysrtc@500a8000 {
364			compatible = "silabs,gecko-stimer";
365			reg = <0x500a8000 0x4000>;
366			interrupts = <70 0>, <71 0>;
367			interrupt-names = "sysrtc_app", "sysrtc_seq";
368			clock-frequency = <32768>;
369			prescaler = <1>;
370			clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>;
371			status = "disabled";
372		};
373
374		gpio: gpio@5003c000 {
375			compatible = "silabs,gecko-gpio";
376			reg = <0x5003c000 0x4000>;
377			interrupts = <27 2>, <26 2>;
378			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
379			clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
380
381			ranges;
382			#address-cells = <1>;
383			#size-cells = <1>;
384
385			gpioa: gpio@5003c030 {
386				compatible = "silabs,gecko-gpio-port";
387				reg = <0x5003c030 0x30>;
388				peripheral-id = <0>;
389				gpio-controller;
390				#gpio-cells = <2>;
391				status = "disabled";
392			};
393
394			gpiob: gpio@5003c060 {
395				compatible = "silabs,gecko-gpio-port";
396				reg = <0x5003c060 0x30>;
397				peripheral-id = <1>;
398				gpio-controller;
399				#gpio-cells = <2>;
400				status = "disabled";
401			};
402
403			gpioc: gpio@5003c090 {
404				compatible = "silabs,gecko-gpio-port";
405				reg = <0x5003c090 0x30>;
406				peripheral-id = <2>;
407				gpio-controller;
408				#gpio-cells = <2>;
409				status = "disabled";
410			};
411
412			gpiod: gpio@5003c0C0 {
413				compatible = "silabs,gecko-gpio-port";
414				reg = <0x5003c0C0 0x30>;
415				peripheral-id = <3>;
416				gpio-controller;
417				#gpio-cells = <2>;
418				status = "disabled";
419			};
420		};
421
422		pinctrl: pin-controller@5003c440 {
423			compatible = "silabs,dbus-pinctrl";
424			reg = <0x5003c440 0xbc0>;
425		};
426
427		dma0: dma@50040000{
428			compatible = "silabs,ldma";
429			reg = <0x50040000 0x4000>;
430			interrupts = <22 0>;
431			#dma-cells = <3>;
432			dma_channels = <8>;
433			status = "disabled";
434		};
435
436		wdog0: wdog@5b004000 {
437			compatible = "silabs,gecko-wdog";
438			reg = <0x5b004000 0x4000>;
439			peripheral-id = <0>;
440			interrupts = <43 0>;
441			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
442			status = "disabled";
443		};
444
445		wdog1: wdog@5b008000 {
446			compatible = "silabs,gecko-wdog";
447			reg = <0x5b008000 0x4000>;
448			peripheral-id = <1>;
449			interrupts = <44 0>;
450			clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
451			status = "disabled";
452		};
453
454		adc0: adc@59004000 {
455			compatible = "silabs,gecko-iadc";
456			reg = <0x59004000 0x4000>;
457			interrupts = <50 0>;
458			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
459			status = "disabled";
460			#io-channel-cells = <1>;
461		};
462
463		dcdc: dcdc@50094000 {
464			compatible = "silabs,series2-dcdc";
465			reg = <0x50094000 0x4000>;
466			interrupts = <54 0>;
467			status = "disabled";
468		};
469	};
470
471	hwinfo: hwinfo {
472		compatible = "silabs,gecko-hwinfo";
473		status = "disabled";
474	};
475};
476
477&nvic {
478	arm,num-irq-priority-bits = <4>;
479};
480