1/*
2 * Copyright (c) 2020 TriaGnoSys GmbH
3 * Copyright (c) 2021 Safran Passenger Innovations Germany GmbH
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <dt-bindings/clock/silabs/xg21-clock.h>
12#include <freq.h>
13
14/ {
15	chosen {
16		zephyr,entropy = &se;
17		zephyr,flash-controller = &msc;
18	};
19
20	clocks {
21		sysclk: sysclk {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&hfrcodpll>;
25		};
26		hclk: hclk {
27			#clock-cells = <0>;
28			compatible = "fixed-factor-clock";
29			clocks = <&sysclk>;
30			/* Divider 1, 2, or 4 */
31			clock-div = <1>;
32		};
33		pclk: pclk {
34			#clock-cells = <0>;
35			compatible = "fixed-factor-clock";
36			clocks = <&hclk>;
37			/* Divider 1 or 2 */
38			clock-div = <2>;
39		};
40		lspclk: lspclk {
41			#clock-cells = <0>;
42			compatible = "fixed-factor-clock";
43			clocks = <&pclk>;
44			/* Divider 1 or 2 */
45			clock-div = <2>;
46		};
47		hclkdiv1024: hclkdiv1024 {
48			#clock-cells = <0>;
49			compatible = "fixed-factor-clock";
50			clocks = <&hclk>;
51			/* Fixed divider of 1024 */
52			clock-div = <1024>;
53		};
54		traceclk: traceclk {
55			#clock-cells = <0>;
56			compatible = "fixed-factor-clock";
57			clocks = <&hclk>;
58		};
59		em01grpaclk: em01grpaclk {
60			#clock-cells = <0>;
61			compatible = "fixed-factor-clock";
62			clocks = <&hfrcodpll>;
63		};
64		iadcclk: iadcclk {
65			#clock-cells = <0>;
66			compatible = "fixed-factor-clock";
67			clocks = <&em01grpaclk>;
68		};
69		em23grpaclk: em23grpaclk {
70			#clock-cells = <0>;
71			compatible = "fixed-factor-clock";
72			clocks = <&lfrco>;
73		};
74		em4grpaclk: em4grpaclk {
75			#clock-cells = <0>;
76			compatible = "fixed-factor-clock";
77			clocks = <&lfrco>;
78		};
79		rtccclk: rtccclk {
80			#clock-cells = <0>;
81			compatible = "fixed-factor-clock";
82			clocks = <&lfrco>;
83		};
84		wdog0clk: wdog0clk {
85			#clock-cells = <0>;
86			compatible = "fixed-factor-clock";
87			clocks = <&lfrco>;
88		};
89		wdog1clk: wdog1clk {
90			#clock-cells = <0>;
91			compatible = "fixed-factor-clock";
92			clocks = <&lfrco>;
93		};
94	};
95
96	cpus {
97		#address-cells = <1>;
98		#size-cells = <0>;
99
100		cpu0: cpu@0 {
101			device_type = "cpu";
102			compatible = "arm,cortex-m33f";
103			reg = <0>;
104			#address-cells = <1>;
105			#size-cells = <1>;
106
107			mpu: mpu@e000ed90 {
108				compatible = "arm,armv8m-mpu";
109				reg = <0xe000ed90 0x40>;
110			};
111		};
112	};
113
114	sram0: memory@20000000 {
115		device_type = "memory";
116		compatible = "mmio-sram";
117	};
118
119	soc {
120		cmu: clock@50008000 {
121			compatible = "silabs,series-clock";
122			reg = <0x50008000 0x4000>;
123			interrupts = <48 0>;
124			interrupt-names = "cmu";
125			status = "okay";
126			#clock-cells = <2>;
127		};
128
129		fsrco: fsrco@50018000 {
130			#clock-cells = <0>;
131			compatible = "fixed-clock";
132			reg = <0x50018000 0x4000>;
133			clock-frequency = <DT_FREQ_M(20)>;
134		};
135
136		clk_hfxo: hfxo: hfxo@5000c000 {
137			#clock-cells = <0>;
138			compatible = "silabs,hfxo";
139			reg = <0x5000c000 0x4000>;
140			interrupts = <45 0>;
141			interrupt-names = "hfxo";
142			clock-frequency = <DT_FREQ_K(38400)>;
143			ctune = <140>;
144			precision = <50>;
145		};
146
147		lfxo: lfxo@50020000 {
148			#clock-cells = <0>;
149			compatible = "silabs,series2-lfxo";
150			reg = <0x50020000 0x4000>;
151			clock-frequency = <32768>;
152			ctune = <63>;
153			precision = <50>;
154			timeout = <4096>;
155			status = "disabled";
156		};
157
158		hfrcodpll: hfrcodpll@50010000 {
159			#clock-cells = <0>;
160			compatible = "silabs,series2-hfrcodpll";
161			reg = <0x50010000 0x4000>;
162			clock-frequency = <DT_FREQ_M(19)>;
163		};
164
165		hfrcoem23: hfrcoem23@5a014000 {
166			#clock-cells = <0>;
167			compatible = "silabs,series2-hfrcoem23";
168			reg = <0x5a014000 0x4000>;
169			clock-frequency = <DT_FREQ_M(19)>;
170		};
171
172		lfrco: lfrco@50024000 {
173			#clock-cells = <0>;
174			compatible = "silabs,series2-lfrco";
175			reg = <0x50024000 0x4000>;
176			clock-frequency = <32768>;
177		};
178
179		ulfrco: ulfrco@50028000 {
180			#clock-cells = <0>;
181			compatible = "fixed-clock";
182			reg = <0x50028000 0x4000>;
183			clock-frequency = <1000>;
184		};
185
186		clkin0: clkin0@5003c46c {
187			#clock-cells = <0>;
188			compatible = "fixed-clock";
189			reg = <0x5003c46c 0x4>;
190			clock-frequency = <DT_FREQ_M(38)>;
191		};
192
193		msc: flash-controller@50030000 {
194			compatible = "silabs,gecko-flash-controller";
195			reg = <0x50030000 0x31a4>;
196			interrupts = <51 0>;
197
198			#address-cells = <1>;
199			#size-cells = <1>;
200
201			flash0: flash@0 {
202				compatible = "soc-nv-flash";
203				write-block-size = <4>;
204				erase-block-size = <8192>;
205			};
206		};
207
208		usart0: usart@50058000 { /* USART0 */
209			compatible = "silabs,gecko-usart";
210			reg = <0x50058000 0x400>;
211			interrupts = <11 0>, <12 0>;
212			interrupt-names = "rx", "tx";
213			peripheral-id = <0>;
214			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
215			status = "disabled";
216		};
217
218		usart1: usart@5005c000 { /* USART1 */
219			compatible = "silabs,gecko-usart";
220			reg = <0x5005c000 0x400>;
221			interrupts = <13 0>, <14 0>;
222			interrupt-names = "rx", "tx";
223			peripheral-id = <1>;
224			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
225			status = "disabled";
226		};
227
228		usart2: usart@50060000 { /* USART2 */
229			compatible = "silabs,gecko-usart";
230			reg = <0x50060000 0x400>;
231			interrupts = <15 0>, <16 0>;
232			interrupt-names = "rx", "tx";
233			peripheral-id = <2>;
234			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
235			status = "disabled";
236		};
237
238		i2c0: i2c@5a010000 {
239			compatible = "silabs,gecko-i2c";
240			clock-frequency = <I2C_BITRATE_STANDARD>;
241			#address-cells = <1>;
242			#size-cells = <0>;
243			reg = <0x5a010000 0x400>;
244			interrupts = <27 0>;
245			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_LSPCLK>;
246			status = "disabled";
247		};
248
249		i2c1: i2c@50068000 {
250			compatible = "silabs,gecko-i2c";
251			clock-frequency = <I2C_BITRATE_STANDARD>;
252			#address-cells = <1>;
253			#size-cells = <0>;
254			reg = <0x50068000 0x400>;
255			interrupts = <28 0>;
256			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
257			status = "disabled";
258		};
259
260		rtcc0: rtcc@58000000 {
261			compatible = "silabs,gecko-stimer";
262			reg = <0x58000000 0x400>;
263			interrupts = <10 0>;
264			interrupt-names = "rtcc";
265			clock-frequency = <32768>;
266			prescaler = <1>;
267			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_RTCCCLK>;
268			status = "disabled";
269		};
270
271		gpio: gpio@5003c300 {
272			compatible = "silabs,gecko-gpio";
273			reg = <0x5003c300 0x440>;
274			interrupts = <26 2>, <25 2>;
275			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
276			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
277
278			ranges;
279			#address-cells = <1>;
280			#size-cells = <1>;
281
282			gpioa: gpio@5003c000 {
283				compatible = "silabs,gecko-gpio-port";
284				reg = <0x5003c000 0x30>;
285				peripheral-id = <0>;
286				gpio-controller;
287				#gpio-cells = <2>;
288				status = "disabled";
289			};
290
291			gpiob: gpio@5003c030 {
292				compatible = "silabs,gecko-gpio-port";
293				reg = <0x5003c030 0x30>;
294				peripheral-id = <1>;
295				gpio-controller;
296				#gpio-cells = <2>;
297				status = "disabled";
298			};
299
300			gpioc: gpio@5003c060 {
301				compatible = "silabs,gecko-gpio-port";
302				reg = <0x5003c060 0x30>;
303				peripheral-id = <2>;
304				gpio-controller;
305				#gpio-cells = <2>;
306				status = "disabled";
307			};
308
309			gpiod: gpio@5003c090 {
310				compatible = "silabs,gecko-gpio-port";
311				reg = <0x5003c090 0x30>;
312				peripheral-id = <3>;
313				gpio-controller;
314				#gpio-cells = <2>;
315				status = "disabled";
316			};
317		};
318
319		pinctrl: pin-controller@5003c440 {
320			compatible = "silabs,dbus-pinctrl";
321			reg = <0x5003c440 0xbc0>;
322		};
323
324		se: semailbox@5c000000 {
325			compatible = "silabs,gecko-semailbox";
326			reg = <0x5c000000 0x80>;
327			interrupts = <0 3>, <1 3>, <2 3>;
328			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
329			status = "okay";
330		};
331
332		dma0: dma@40040000{
333			compatible = "silabs,ldma";
334			reg = <0x40040000 0x4000>;
335			interrupts = <21 0>;
336			#dma-cells = <3>;
337			dma_channels = <8>;
338			status = "disabled";
339		};
340
341		wdog0: wdog@5a018000 {
342			compatible = "silabs,gecko-wdog";
343			reg = <0x5a018000 0x2C>;
344			peripheral-id = <0>;
345			interrupts = <43 0>;
346			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG0CLK>;
347			status = "disabled";
348		};
349
350		wdog1: wdog@5a01c000 {
351			compatible = "silabs,gecko-wdog";
352			reg = <0x5a01c000 0x2C>;
353			peripheral-id = <1>;
354			interrupts = <44 0>;
355			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG1CLK>;
356			status = "disabled";
357		};
358	};
359};
360
361&nvic {
362	arm,num-irq-priority-bits = <4>;
363};
364