1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <freq.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
14	model = "sifive,FU540";
15
16	clocks {
17		coreclk: core-clk {
18			#clock-cells = <0>;
19			compatible = "fixed-clock";
20			clock-frequency = <DT_FREQ_M(1000)>;
21		};
22
23		tlclk: tl-clk {
24			#clock-cells = <0>;
25			compatible = "fixed-factor-clock";
26			clocks = <&coreclk>;
27			clock-div = <2>;
28		};
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu: cpu@0 {
36			compatible = "sifive,e51";
37			device_type = "cpu";
38			reg = <0>;
39			riscv,isa = "rv64imac_zicsr_zifencei";
40			status = "okay";
41
42			hlic: interrupt-controller {
43				compatible = "riscv,cpu-intc";
44				#address-cells = <0>;
45				#interrupt-cells = <1>;
46				interrupt-controller;
47			};
48		};
49	};
50
51	soc {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		compatible = "simple-bus";
55		ranges;
56
57		modeselect: rom@1000 {
58			compatible = "sifive,modeselect0";
59			reg = <0x1000 0x1000>;
60			reg-names = "mem";
61		};
62
63		maskrom: rom@10000 {
64			compatible = "sifive,maskrom0";
65			reg = <0x10000 0x8000>;
66			reg-names = "mem";
67		};
68
69		dtim: dtim@1000000 {
70			compatible = "sifive,dtim0";
71			reg = <0x1000000 0x2000>;
72			reg-names = "mem";
73		};
74
75		itim0: itim0@1800000 {
76			compatible = "sifive,itim0";
77			reg = <0x1800000 0x2000>;
78			reg-names = "mem";
79		};
80
81		itim1: itim1@1808000 {
82			compatible = "sifive,itim0";
83			reg = <0x1808000 0x7000>;
84			reg-names = "mem";
85		};
86
87		itim2: itim2@1810000 {
88			compatible = "sifive,itim0";
89			reg = <0x1810000 0x7000>;
90			reg-names = "mem";
91		};
92
93		itim3: itim3@1818000 {
94			compatible = "sifive,itim0";
95			reg = <0x1818000 0x7000>;
96			reg-names = "mem";
97		};
98
99		itim4: itim4@1820000 {
100			compatible = "sifive,itim0";
101			reg = <0x1820000 0x7000>;
102			reg-names = "mem";
103		};
104
105		clint: clint@2000000 {
106			compatible = "sifive,clint0";
107			interrupts-extended = <&hlic 3 &hlic 7>;
108			reg = <0x2000000 0x10000>;
109		};
110
111		l2lim: l2lim@8000000 {
112			compatible = "sifive,l2lim0";
113			reg = <0x8000000 0x2000000>;
114			reg-names = "mem";
115		};
116
117		plic: interrupt-controller@c000000 {
118			compatible = "sifive,plic-1.0.0";
119			#address-cells = <0>;
120			#interrupt-cells = <2>;
121			interrupt-controller;
122			interrupts-extended = <&hlic 11>;
123			reg = <0x0c000000 0x04000000>;
124			riscv,max-priority = <7>;
125			riscv,ndev = <52>;
126		};
127
128		uart0: serial@10010000 {
129			compatible = "sifive,uart0";
130			interrupt-parent = <&plic>;
131			interrupts = <4 1>;
132			reg = <0x10010000 0x1000>;
133			reg-names = "control";
134			status = "disabled";
135		};
136
137		uart1: serial@10011000 {
138			compatible = "sifive,uart0";
139			interrupt-parent = <&plic>;
140			interrupts = <5 1>;
141			reg = <0x10011000 0x1000>;
142			reg-names = "control";
143			status = "disabled";
144		};
145
146		spi0: spi@10040000 {
147			compatible = "sifive,spi0";
148			interrupt-parent = <&plic>;
149			interrupts = <51 1>;
150			reg = <0x10040000 0x1000 0x20000000 0x10000000>;
151			reg-names = "control", "mem";
152			status = "disabled";
153			#address-cells = <1>;
154			#size-cells = <0>;
155		};
156
157		spi1: spi@10041000 {
158			compatible = "sifive,spi0";
159			interrupt-parent = <&plic>;
160			interrupts = <52 1>;
161			reg = <0x10041000 0x1000>;
162			reg-names = "control";
163			status = "disabled";
164			#address-cells = <1>;
165			#size-cells = <0>;
166		};
167
168		spi2: spi@10050000 {
169			compatible = "sifive,spi0";
170			interrupt-parent = <&plic>;
171			interrupts = <6 1>;
172			reg = <0x10050000 0x1000>;
173			reg-names = "control";
174			status = "disabled";
175			#address-cells = <1>;
176			#size-cells = <0>;
177		};
178
179		gpio0: gpio@10060000 {
180			compatible = "sifive,gpio0";
181			gpio-controller;
182			interrupt-parent = <&plic>;
183			interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
184				<11 1>, <12 1>, <13 1>, <14 1>,
185				<15 1>, <16 1>, <17 1>, <18 1>,
186				<19 1>, <20 1>, <21 1>, <22 1>;
187			reg = <0x10060000 0x1000>;
188			reg-names = "control";
189			status = "disabled";
190			#gpio-cells = <2>;
191
192			#address-cells = <1>;
193			#size-cells = <1>;
194			ranges;
195		};
196	};
197};
198