1// shared-reset-vector.S  --  Sharable Reset Vector (requires PRID option)
2
3// Copyright (c) 1999-2010 Tensilica Inc.
4//
5// Permission is hereby granted, free of charge, to any person obtaining
6// a copy of this software and associated documentation files (the
7// "Software"), to deal in the Software without restriction, including
8// without limitation the rights to use, copy, modify, merge, publish,
9// distribute, sublicense, and/or sell copies of the Software, and to
10// permit persons to whom the Software is furnished to do so, subject to
11// the following conditions:
12//
13// The above copyright notice and this permission notice shall be included
14// in all copies or substantial portions of the Software.
15//
16// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23
24#include <xtensa/coreasm.h>
25
26	//  Populate this processor's entry in the reset table.
27	//  The core instance specific LSP should put this section
28	//  in the correct location within the table.
29	//
30	.section .ResetTable.rodata, "a"
31	.word	_ResetHandler
32
33	//  This sharable reset code assumes RC-2009.0 or later hardware,
34	//  to guarantee that no processor state initialization is required
35	//  prior to doing loads etc.
36	//  Total size is 28 bytes (or 27 with density option).
37	//  By necessity, none of these bytes vary by core instance;
38	//  the appropriate reset table entry is selected using PRID.
39	//
40#if XCHAL_HAVE_PRID
41	.section .SharedResetVector.text, "ax"
42	.begin	no-absolute-literals
43
44	.align	4
45	.global	_SharedResetVector
46_SharedResetVector:
47	j	.LSharedResetHandler
48
49	.align	4
50	.literal_position
51
52	// Use L32R if available
53#if XCHAL_HAVE_L32R
54	.literal rtbase, _ResetTable_base
55#endif
56
57	.align	4
58.LSharedResetHandler:
59	rsr.prid   a0		// get processor ID (16 bits)
60#if XCHAL_HAVE_L32R
61	l32r	a1, rtbase	// force use of L32R
62#else
63	movi    a1, _ResetTable_base	// No L32R, will likely become CONST16
64#endif
65	extui	a0, a0, 0, 4	// ID of core within the multiprocessor (FIXME: need proper constant...)
66	addx4	a1, a0, a1
67	l32i	a1, a1, 0
68	jx	a1		// jump to core-specific initialization
69
70	.size	_SharedResetVector, . - _SharedResetVector
71	.end	no-absolute-literals
72#endif
73
74