1 /*
2 * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <plat/arm/common/plat_arm.h>
12 #include <plat/common/platform.h>
13 #include <drivers/arm/sbsa.h>
14
15 #if SPM_MM
16 #include <services/spm_mm_partition.h>
17 #endif
18
19 /*
20 * Table of regions for different BL stages to map using the MMU.
21 */
22 #if IMAGE_BL1
23 const mmap_region_t plat_arm_mmap[] = {
24 ARM_MAP_SHARED_RAM,
25 SGI_MAP_FLASH0_RO,
26 CSS_SGI_MAP_DEVICE,
27 SOC_PLATFORM_PERIPH_MAP_DEVICE,
28 SOC_SYSTEM_PERIPH_MAP_DEVICE,
29 {0}
30 };
31 #endif
32
33 #if IMAGE_BL2
34 const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 SGI_MAP_FLASH0_RO,
37 #ifdef PLAT_ARM_MEM_PROT_ADDR
38 ARM_V2M_MAP_MEM_PROTECT,
39 #endif
40 CSS_SGI_MAP_DEVICE,
41 SOC_MEMCNTRL_MAP_DEVICE,
42 SOC_PLATFORM_PERIPH_MAP_DEVICE,
43 SOC_SYSTEM_PERIPH_MAP_DEVICE,
44 ARM_MAP_NS_DRAM1,
45 #if CSS_SGI_CHIP_COUNT > 1
46 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
47 #endif
48 #if CSS_SGI_CHIP_COUNT > 2
49 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
50 #endif
51 #if CSS_SGI_CHIP_COUNT > 3
52 SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
53 #endif
54 #if ARM_BL31_IN_DRAM
55 ARM_MAP_BL31_SEC_DRAM,
56 #endif
57 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
58 ARM_SP_IMAGE_MMAP,
59 #endif
60 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
61 ARM_MAP_BL1_RW,
62 #endif
63 {0}
64 };
65 #endif
66
67 #if IMAGE_BL31
68 const mmap_region_t plat_arm_mmap[] = {
69 ARM_MAP_SHARED_RAM,
70 #ifdef PLAT_ARM_MEM_PROT_ADDR
71 ARM_V2M_MAP_MEM_PROTECT,
72 #endif
73 CSS_SGI_MAP_DEVICE,
74 SOC_PLATFORM_PERIPH_MAP_DEVICE,
75 SOC_SYSTEM_PERIPH_MAP_DEVICE,
76 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
77 ARM_SPM_BUF_EL3_MMAP,
78 #endif
79 {0}
80 };
81
82 #if SPM_MM && defined(IMAGE_BL31)
83 const mmap_region_t plat_arm_secure_partition_mmap[] = {
84 PLAT_ARM_SECURE_MAP_SYSTEMREG,
85 PLAT_ARM_SECURE_MAP_NOR2,
86 SOC_PLATFORM_SECURE_UART,
87 SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
88 ARM_SP_IMAGE_MMAP,
89 ARM_SP_IMAGE_NS_BUF_MMAP,
90 #if ENABLE_FEAT_RAS && FFH_SUPPORT
91 CSS_SGI_SP_CPER_BUF_MMAP,
92 #endif
93 ARM_SP_IMAGE_RW_MMAP,
94 ARM_SPM_BUF_EL0_MMAP,
95 {0}
96 };
97 #endif /* SPM_MM && defined(IMAGE_BL31) */
98 #endif
99
100 ARM_CASSERT_MMAP
101
102 #if SPM_MM && defined(IMAGE_BL31)
103 /*
104 * Boot information passed to a secure partition during initialisation. Linear
105 * indices in MP information will be filled at runtime.
106 */
107 static spm_mm_mp_info_t sp_mp_info[] = {
108 [0] = {0x81000000, 0},
109 [1] = {0x81010000, 0},
110 [2] = {0x81020000, 0},
111 [3] = {0x81030000, 0},
112 [4] = {0x81040000, 0},
113 [5] = {0x81050000, 0},
114 [6] = {0x81060000, 0},
115 [7] = {0x81070000, 0},
116 [8] = {0x81080000, 0},
117 [9] = {0x81090000, 0},
118 [10] = {0x810a0000, 0},
119 [11] = {0x810b0000, 0},
120 [12] = {0x810c0000, 0},
121 [13] = {0x810d0000, 0},
122 [14] = {0x810e0000, 0},
123 [15] = {0x810f0000, 0},
124 };
125
126 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
127 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
128 .h.version = VERSION_1,
129 .h.size = sizeof(spm_mm_boot_info_t),
130 .h.attr = 0,
131 .sp_mem_base = ARM_SP_IMAGE_BASE,
132 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
133 .sp_image_base = ARM_SP_IMAGE_BASE,
134 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
135 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
136 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
137 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
138 .sp_image_size = ARM_SP_IMAGE_SIZE,
139 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
140 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
141 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
142 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
143 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
144 .num_cpus = PLATFORM_CORE_COUNT,
145 .mp_info = &sp_mp_info[0],
146 };
147
plat_get_secure_partition_mmap(void * cookie)148 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
149 {
150 return plat_arm_secure_partition_mmap;
151 }
152
plat_get_secure_partition_boot_info(void * cookie)153 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
154 void *cookie)
155 {
156 return &plat_arm_secure_partition_boot_info;
157 }
158 #endif /* SPM_MM && defined(IMAGE_BL31) */
159
160 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)161 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
162 {
163 assert(heap_addr != NULL);
164 assert(heap_size != NULL);
165
166 return arm_get_mbedtls_heap(heap_addr, heap_size);
167 }
168 #endif
169
plat_arm_secure_wdt_start(void)170 void plat_arm_secure_wdt_start(void)
171 {
172 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
173 }
174
plat_arm_secure_wdt_stop(void)175 void plat_arm_secure_wdt_stop(void)
176 {
177 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
178 }
179
