1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * This file has been automatically generated 9 * Tool Version: 1.0.0 10 * Generation Date: 2023-08-07 11 */ 12 13 #ifndef _SEDI_UART_REGS_H_ 14 #define _SEDI_UART_REGS_H_ 15 16 #include <sedi_reg_defs.h> 17 18 19 /* ********* UART RBR *********** 20 * 21 * Register of SEDI UART 22 * RBR: Receive Buffer Register 23 * AddressOffset : 0x0 24 * AccessType : RW 25 * WritableBitMask: 0xffffffff 26 * ResetValue : (uint32_t)0x0 27 */ 28 SEDI_REG_DEFINE(UART, RBR, 0x0, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 29 30 /* 31 * Bit Field of Register RBR 32 * 33 * BitOffset : 34 * BitWidth : 35 * AccessType: 36 * ResetValue: 37 */ 38 39 /* ********* UART IER *********** 40 * 41 * Register of SEDI UART 42 * IER: Interrupt Enable Register 43 * AddressOffset : 0x4 44 * AccessType : RW 45 * WritableBitMask: 0xffffffff 46 * ResetValue : (uint32_t)0x0 47 */ 48 SEDI_REG_DEFINE(UART, IER, 0x4, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 49 50 /** 51 * TODO: 52 * the IER register field definitions are missing in the osxml file, 53 * manually added, should fix it in the osxml input. 54 **/ 55 SEDI_RBF_DEFINE(UART, IER, ERBFI, 0, 1, RW, (uint32_t)0x0); 56 SEDI_RBFV_DEFINE(UART, IER, ERBFI, DISABLE, 0x0); 57 SEDI_RBFV_DEFINE(UART, IER, ERBFI, ENABLE, 0x1); 58 59 SEDI_RBF_DEFINE(UART, IER, ETBEI, 1, 1, RW, (uint32_t)0x0); 60 SEDI_RBFV_DEFINE(UART, IER, ETBEI, DISABLE, 0x0); 61 SEDI_RBFV_DEFINE(UART, IER, ETBEI, ENABLE, 0x1); 62 63 SEDI_RBF_DEFINE(UART, IER, ELSI, 2, 1, RW, (uint32_t)0x0); 64 SEDI_RBFV_DEFINE(UART, IER, ELSI, DISABLE, 0x9); 65 SEDI_RBFV_DEFINE(UART, IER, ELSI, ENABLE, 0x1); 66 67 SEDI_RBF_DEFINE(UART, IER, PTIME, 7, 1, RW, (uint32_t)0x0); 68 SEDI_RBFV_DEFINE(UART, IER, PTIME, DISABLE, 0x0); 69 SEDI_RBFV_DEFINE(UART, IER, PTIME, ENABLE, 0x1); 70 71 /* 72 * Bit Field of Register IER 73 * 74 * BitOffset : 75 * BitWidth : 76 * AccessType: 77 * ResetValue: 78 */ 79 80 /* ********* UART IIR *********** 81 * 82 * Register of SEDI UART 83 * IIR: Interrupt Identification Register 84 * AddressOffset : 0x8 85 * AccessType : RW 86 * WritableBitMask: 0xffffffff 87 * ResetValue : (uint32_t)0x0 88 */ 89 SEDI_REG_DEFINE(UART, IIR, 0x8, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 90 /** 91 * TODO: 92 * the IIR register field definitions are missing in the osxml file, 93 * manually added, should fix it in the osxml input. 94 **/ 95 SEDI_RBF_DEFINE(UART, IIR, FIFOE, 0, 1, RW, (uint32_t)0x0); 96 SEDI_RBFV_DEFINE(UART, IIR, FIFOE, DISABLE, 0x0); 97 SEDI_RBFV_DEFINE(UART, IIR, FIFOE, ENABLE, 0x1); 98 99 SEDI_RBF_DEFINE(UART, IIR, RFIFOR, 1, 1, RW, (uint32_t)0x0); 100 SEDI_RBFV_DEFINE(UART, IIR, RFIFOR, DISABLE, 0x0); 101 SEDI_RBFV_DEFINE(UART, IIR, RFIFOR, ENABLE, 0x1); 102 103 SEDI_RBF_DEFINE(UART, IIR, XFIFOR, 2, 1, RW, (uint32_t)0x0); 104 SEDI_RBFV_DEFINE(UART, IIR, XFIFOR, DISABLE, 0x0); 105 SEDI_RBFV_DEFINE(UART, IIR, XFIFOR, ENABLE, 0x1); 106 107 SEDI_RBF_DEFINE(UART, IIR, IID, 0, 4, RO, 0); 108 109 /* 110 * Bit Field of Register IIR 111 * 112 * BitOffset : 113 * BitWidth : 114 * AccessType: 115 * ResetValue: 116 */ 117 118 /* ********* UART LCR *********** 119 * 120 * Register of SEDI UART 121 * LCR: Line Control Register 122 * AddressOffset : 0xc 123 * AccessType : RW 124 * WritableBitMask: 0xff 125 * ResetValue : (uint32_t)0x0 126 */ 127 SEDI_REG_DEFINE(UART, LCR, 0xc, RW, (uint32_t)0xff, (uint32_t)0x0); 128 129 /* 130 * Bit Field of Register LCR 131 * DLS: 132 * BitOffset : 0 133 * BitWidth : 2 134 * AccessType: RW 135 * ResetValue: (uint32_t)0x0 136 */ 137 SEDI_RBF_DEFINE(UART, LCR, DLS, 0, 2, RW, (uint32_t)0x0); 138 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_5BITS, 0x0); 139 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_6BITS, 0x1); 140 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_7BITS, 0x2); 141 SEDI_RBFV_DEFINE(UART, LCR, DLS, CHAR_8BITS, 0x3); 142 143 /* 144 * Bit Field of Register LCR 145 * STOP: 146 * BitOffset : 2 147 * BitWidth : 1 148 * AccessType: RW 149 * ResetValue: (uint32_t)0x0 150 */ 151 SEDI_RBF_DEFINE(UART, LCR, STOP, 2, 1, RW, (uint32_t)0x0); 152 SEDI_RBFV_DEFINE(UART, LCR, STOP, STOP_1BIT, 0x0); 153 SEDI_RBFV_DEFINE(UART, LCR, STOP, STOP_1_5BIT_OR_2BIT, 0x1); 154 155 /* 156 * Bit Field of Register LCR 157 * PEN: 158 * BitOffset : 3 159 * BitWidth : 1 160 * AccessType: RW 161 * ResetValue: (uint32_t)0x0 162 */ 163 SEDI_RBF_DEFINE(UART, LCR, PEN, 3, 1, RW, (uint32_t)0x0); 164 SEDI_RBFV_DEFINE(UART, LCR, PEN, DISABLED, 0x0); 165 SEDI_RBFV_DEFINE(UART, LCR, PEN, ENABLED, 0x1); 166 167 /* 168 * Bit Field of Register LCR 169 * EPS: 170 * BitOffset : 4 171 * BitWidth : 1 172 * AccessType: RW 173 * ResetValue: (uint32_t)0x0 174 */ 175 SEDI_RBF_DEFINE(UART, LCR, EPS, 4, 1, RW, (uint32_t)0x0); 176 SEDI_RBFV_DEFINE(UART, LCR, EPS, EVEN_PARITY, 0x1); 177 SEDI_RBFV_DEFINE(UART, LCR, EPS, ODD_PARITY, 0x0); 178 179 /* 180 * Bit Field of Register LCR 181 * SP: 182 * BitOffset : 5 183 * BitWidth : 1 184 * AccessType: RW 185 * ResetValue: (uint32_t)0x0 186 */ 187 SEDI_RBF_DEFINE(UART, LCR, SP, 5, 1, RW, (uint32_t)0x0); 188 SEDI_RBFV_DEFINE(UART, LCR, SP, DISABLED, 0x0); 189 SEDI_RBFV_DEFINE(UART, LCR, SP, ENABLED, 0x1); 190 191 /* 192 * Bit Field of Register LCR 193 * BC: 194 * BitOffset : 6 195 * BitWidth : 1 196 * AccessType: RW 197 * ResetValue: (uint32_t)0x0 198 */ 199 SEDI_RBF_DEFINE(UART, LCR, BC, 6, 1, RW, (uint32_t)0x0); 200 SEDI_RBFV_DEFINE(UART, LCR, BC, DISABLED, 0x0); 201 SEDI_RBFV_DEFINE(UART, LCR, BC, ENABLED, 0x1); 202 203 /* 204 * Bit Field of Register LCR 205 * DLAB: 206 * BitOffset : 7 207 * BitWidth : 1 208 * AccessType: RW 209 * ResetValue: (uint32_t)0x0 210 */ 211 SEDI_RBF_DEFINE(UART, LCR, DLAB, 7, 1, RW, (uint32_t)0x0); 212 SEDI_RBFV_DEFINE(UART, LCR, DLAB, DISABLED, 0x0); 213 SEDI_RBFV_DEFINE(UART, LCR, DLAB, ENABLED, 0x1); 214 215 /* 216 * Bit Field of Register LCR 217 * RSVD_LCR_31to8: 218 * BitOffset : 8 219 * BitWidth : 24 220 * AccessType: RO 221 * ResetValue: (uint32_t)0x0 222 */ 223 SEDI_RBF_DEFINE(UART, LCR, RSVD_LCR_31to8, 8, 24, RO, (uint32_t)0x0); 224 225 /* ********* UART MCR *********** 226 * 227 * Register of SEDI UART 228 * MCR: Modem Control Register 229 * AddressOffset : 0x10 230 * AccessType : RW 231 * WritableBitMask: 0x3f 232 * ResetValue : (uint32_t)0x0 233 */ 234 SEDI_REG_DEFINE(UART, MCR, 0x10, RW, (uint32_t)0x3f, (uint32_t)0x0); 235 236 /* 237 * Bit Field of Register MCR 238 * DTR: 239 * BitOffset : 0 240 * BitWidth : 1 241 * AccessType: RW 242 * ResetValue: (uint32_t)0x0 243 */ 244 SEDI_RBF_DEFINE(UART, MCR, DTR, 0, 1, RW, (uint32_t)0x0); 245 SEDI_RBFV_DEFINE(UART, MCR, DTR, ACTIVE, 0x1); 246 SEDI_RBFV_DEFINE(UART, MCR, DTR, INACTIVE, 0x0); 247 248 /* 249 * Bit Field of Register MCR 250 * RTS: 251 * BitOffset : 1 252 * BitWidth : 1 253 * AccessType: RW 254 * ResetValue: (uint32_t)0x0 255 */ 256 SEDI_RBF_DEFINE(UART, MCR, RTS, 1, 1, RW, (uint32_t)0x0); 257 SEDI_RBFV_DEFINE(UART, MCR, RTS, ACTIVE, 0x1); 258 SEDI_RBFV_DEFINE(UART, MCR, RTS, INACTIVE, 0x0); 259 260 /* 261 * Bit Field of Register MCR 262 * OUT1: 263 * BitOffset : 2 264 * BitWidth : 1 265 * AccessType: RW 266 * ResetValue: (uint32_t)0x0 267 */ 268 SEDI_RBF_DEFINE(UART, MCR, OUT1, 2, 1, RW, (uint32_t)0x0); 269 SEDI_RBFV_DEFINE(UART, MCR, OUT1, OUT1_0, 0x0); 270 SEDI_RBFV_DEFINE(UART, MCR, OUT1, OUT1_1, 0x1); 271 272 /* 273 * Bit Field of Register MCR 274 * OUT2: 275 * BitOffset : 3 276 * BitWidth : 1 277 * AccessType: RW 278 * ResetValue: (uint32_t)0x0 279 */ 280 SEDI_RBF_DEFINE(UART, MCR, OUT2, 3, 1, RW, (uint32_t)0x0); 281 SEDI_RBFV_DEFINE(UART, MCR, OUT2, OUT2_0, 0x0); 282 SEDI_RBFV_DEFINE(UART, MCR, OUT2, OUT2_1, 0x1); 283 284 /* 285 * Bit Field of Register MCR 286 * LoopBack: 287 * BitOffset : 4 288 * BitWidth : 1 289 * AccessType: RW 290 * ResetValue: (uint32_t)0x0 291 */ 292 SEDI_RBF_DEFINE(UART, MCR, LoopBack, 4, 1, RW, (uint32_t)0x0); 293 SEDI_RBFV_DEFINE(UART, MCR, LoopBack, DISABLED, 0x0); 294 SEDI_RBFV_DEFINE(UART, MCR, LoopBack, ENABLED, 0x1); 295 296 /* 297 * Bit Field of Register MCR 298 * AFCE: 299 * BitOffset : 5 300 * BitWidth : 1 301 * AccessType: RW 302 * ResetValue: (uint32_t)0x0 303 */ 304 SEDI_RBF_DEFINE(UART, MCR, AFCE, 5, 1, RW, (uint32_t)0x0); 305 SEDI_RBFV_DEFINE(UART, MCR, AFCE, DISABLED, 0x0); 306 SEDI_RBFV_DEFINE(UART, MCR, AFCE, ENABLED, 0x1); 307 308 /* 309 * Bit Field of Register MCR 310 * SIRE: 311 * BitOffset : 6 312 * BitWidth : 1 313 * AccessType: RO 314 * ResetValue: (uint32_t)0x0 315 */ 316 SEDI_RBF_DEFINE(UART, MCR, SIRE, 6, 1, RO, (uint32_t)0x0); 317 SEDI_RBFV_DEFINE(UART, MCR, SIRE, DISABLED, 0x0); 318 SEDI_RBFV_DEFINE(UART, MCR, SIRE, ENABLED, 0x1); 319 320 /* 321 * Bit Field of Register MCR 322 * RSVD_MCR_31to7: 323 * BitOffset : 7 324 * BitWidth : 25 325 * AccessType: RO 326 * ResetValue: (uint32_t)0x0 327 */ 328 SEDI_RBF_DEFINE(UART, MCR, RSVD_MCR_31to7, 7, 25, RO, (uint32_t)0x0); 329 330 /* ********* UART LSR *********** 331 * 332 * Register of SEDI UART 333 * LSR: Line Status Register 334 * AddressOffset : 0x14 335 * AccessType : RO 336 * WritableBitMask: 0x0 337 * ResetValue : (uint32_t)0x60 338 */ 339 SEDI_REG_DEFINE(UART, LSR, 0x14, RO, (uint32_t)0x0, (uint32_t)0x60); 340 341 /* 342 * Bit Field of Register LSR 343 * DR: 344 * BitOffset : 0 345 * BitWidth : 1 346 * AccessType: RO 347 * ResetValue: (uint32_t)0x0 348 */ 349 SEDI_RBF_DEFINE(UART, LSR, DR, 0, 1, RO, (uint32_t)0x0); 350 SEDI_RBFV_DEFINE(UART, LSR, DR, NOT_READY, 0x0); 351 SEDI_RBFV_DEFINE(UART, LSR, DR, READY, 0x1); 352 353 /* 354 * Bit Field of Register LSR 355 * OE: 356 * BitOffset : 1 357 * BitWidth : 1 358 * AccessType: RO 359 * ResetValue: (uint32_t)0x0 360 */ 361 SEDI_RBF_DEFINE(UART, LSR, OE, 1, 1, RO, (uint32_t)0x0); 362 SEDI_RBFV_DEFINE(UART, LSR, OE, NO_OVER_RUN_ERROR, 0x0); 363 SEDI_RBFV_DEFINE(UART, LSR, OE, OVER_RUN_ERROR, 0x1); 364 365 /* 366 * Bit Field of Register LSR 367 * PE: 368 * BitOffset : 2 369 * BitWidth : 1 370 * AccessType: RO 371 * ResetValue: (uint32_t)0x0 372 */ 373 SEDI_RBF_DEFINE(UART, LSR, PE, 2, 1, RO, (uint32_t)0x0); 374 SEDI_RBFV_DEFINE(UART, LSR, PE, NO_PARITY_ERROR, 0x0); 375 SEDI_RBFV_DEFINE(UART, LSR, PE, PARITY_ERROR, 0x1); 376 377 /* 378 * Bit Field of Register LSR 379 * FE: 380 * BitOffset : 3 381 * BitWidth : 1 382 * AccessType: RO 383 * ResetValue: (uint32_t)0x0 384 */ 385 SEDI_RBF_DEFINE(UART, LSR, FE, 3, 1, RO, (uint32_t)0x0); 386 SEDI_RBFV_DEFINE(UART, LSR, FE, FRAMING_ERROR, 0x1); 387 SEDI_RBFV_DEFINE(UART, LSR, FE, NO_FRAMING_ERROR, 0x0); 388 389 /* 390 * Bit Field of Register LSR 391 * BI: 392 * BitOffset : 4 393 * BitWidth : 1 394 * AccessType: RO 395 * ResetValue: (uint32_t)0x0 396 */ 397 SEDI_RBF_DEFINE(UART, LSR, BI, 4, 1, RO, (uint32_t)0x0); 398 SEDI_RBFV_DEFINE(UART, LSR, BI, BREAK, 0x1); 399 SEDI_RBFV_DEFINE(UART, LSR, BI, NO_BREAK, 0x0); 400 401 /* 402 * Bit Field of Register LSR 403 * THRE: 404 * BitOffset : 5 405 * BitWidth : 1 406 * AccessType: RO 407 * ResetValue: (uint32_t)0x1 408 */ 409 SEDI_RBF_DEFINE(UART, LSR, THRE, 5, 1, RO, (uint32_t)0x1); 410 SEDI_RBFV_DEFINE(UART, LSR, THRE, DISABLED, 0x0); 411 SEDI_RBFV_DEFINE(UART, LSR, THRE, ENABLED, 0x1); 412 413 /* 414 * Bit Field of Register LSR 415 * TEMT: 416 * BitOffset : 6 417 * BitWidth : 1 418 * AccessType: RO 419 * ResetValue: (uint32_t)0x1 420 */ 421 SEDI_RBF_DEFINE(UART, LSR, TEMT, 6, 1, RO, (uint32_t)0x1); 422 SEDI_RBFV_DEFINE(UART, LSR, TEMT, DISABLED, 0x0); 423 SEDI_RBFV_DEFINE(UART, LSR, TEMT, ENABLED, 0x1); 424 425 /* 426 * Bit Field of Register LSR 427 * RFE: 428 * BitOffset : 7 429 * BitWidth : 1 430 * AccessType: RO 431 * ResetValue: (uint32_t)0x0 432 */ 433 SEDI_RBF_DEFINE(UART, LSR, RFE, 7, 1, RO, (uint32_t)0x0); 434 SEDI_RBFV_DEFINE(UART, LSR, RFE, NO_RX_FIFO_ERROR, 0x0); 435 SEDI_RBFV_DEFINE(UART, LSR, RFE, RX_FIFO_ERROR, 0x1); 436 437 /* 438 * Bit Field of Register LSR 439 * ADDR_RCVD: 440 * BitOffset : 8 441 * BitWidth : 1 442 * AccessType: RO 443 * ResetValue: (uint32_t)0x0 444 */ 445 SEDI_RBF_DEFINE(UART, LSR, ADDR_RCVD, 8, 1, RO, (uint32_t)0x0); 446 SEDI_RBFV_DEFINE(UART, LSR, ADDR_RCVD, 0, 0); 447 SEDI_RBFV_DEFINE(UART, LSR, ADDR_RCVD, 1, 1); 448 449 /* 450 * Bit Field of Register LSR 451 * RSVD_LSR_31to9: 452 * BitOffset : 9 453 * BitWidth : 23 454 * AccessType: RO 455 * ResetValue: (uint32_t)0x0 456 */ 457 SEDI_RBF_DEFINE(UART, LSR, RSVD_LSR_31to9, 9, 23, RO, (uint32_t)0x0); 458 459 /* ********* UART MSR *********** 460 * 461 * Register of SEDI UART 462 * MSR: Modem Status Register 463 * AddressOffset : 0x18 464 * AccessType : RO 465 * WritableBitMask: 0x0 466 * ResetValue : (uint32_t)0x0 467 */ 468 SEDI_REG_DEFINE(UART, MSR, 0x18, RO, (uint32_t)0x0, (uint32_t)0x0); 469 470 /* 471 * Bit Field of Register MSR 472 * DCTS: 473 * BitOffset : 0 474 * BitWidth : 1 475 * AccessType: RO 476 * ResetValue: (uint32_t)0x0 477 */ 478 SEDI_RBF_DEFINE(UART, MSR, DCTS, 0, 1, RO, (uint32_t)0x0); 479 SEDI_RBFV_DEFINE(UART, MSR, DCTS, CHANGE, 0x1); 480 SEDI_RBFV_DEFINE(UART, MSR, DCTS, NO_CHANGE, 0x0); 481 482 /* 483 * Bit Field of Register MSR 484 * DDSR: 485 * BitOffset : 1 486 * BitWidth : 1 487 * AccessType: RO 488 * ResetValue: (uint32_t)0x0 489 */ 490 SEDI_RBF_DEFINE(UART, MSR, DDSR, 1, 1, RO, (uint32_t)0x0); 491 SEDI_RBFV_DEFINE(UART, MSR, DDSR, CHANGE, 0x1); 492 SEDI_RBFV_DEFINE(UART, MSR, DDSR, NO_CHANGE, 0x0); 493 494 /* 495 * Bit Field of Register MSR 496 * TERI: 497 * BitOffset : 2 498 * BitWidth : 1 499 * AccessType: RO 500 * ResetValue: (uint32_t)0x0 501 */ 502 SEDI_RBF_DEFINE(UART, MSR, TERI, 2, 1, RO, (uint32_t)0x0); 503 SEDI_RBFV_DEFINE(UART, MSR, TERI, CHANGE, 0x1); 504 SEDI_RBFV_DEFINE(UART, MSR, TERI, NO_CHANGE, 0x0); 505 506 /* 507 * Bit Field of Register MSR 508 * DDCD: 509 * BitOffset : 3 510 * BitWidth : 1 511 * AccessType: RO 512 * ResetValue: (uint32_t)0x0 513 */ 514 SEDI_RBF_DEFINE(UART, MSR, DDCD, 3, 1, RO, (uint32_t)0x0); 515 SEDI_RBFV_DEFINE(UART, MSR, DDCD, CHANGE, 0x1); 516 SEDI_RBFV_DEFINE(UART, MSR, DDCD, NO_CHANGE, 0x0); 517 518 /* 519 * Bit Field of Register MSR 520 * CTS: 521 * BitOffset : 4 522 * BitWidth : 1 523 * AccessType: RO 524 * ResetValue: (uint32_t)0x0 525 */ 526 SEDI_RBF_DEFINE(UART, MSR, CTS, 4, 1, RO, (uint32_t)0x0); 527 SEDI_RBFV_DEFINE(UART, MSR, CTS, ASSERTED, 0x1); 528 SEDI_RBFV_DEFINE(UART, MSR, CTS, DEASSERTED, 0x0); 529 530 /* 531 * Bit Field of Register MSR 532 * DSR: 533 * BitOffset : 5 534 * BitWidth : 1 535 * AccessType: RO 536 * ResetValue: (uint32_t)0x0 537 */ 538 SEDI_RBF_DEFINE(UART, MSR, DSR, 5, 1, RO, (uint32_t)0x0); 539 SEDI_RBFV_DEFINE(UART, MSR, DSR, ASSERTED, 0x1); 540 SEDI_RBFV_DEFINE(UART, MSR, DSR, DEASSERTED, 0x0); 541 542 /* 543 * Bit Field of Register MSR 544 * RI: 545 * BitOffset : 6 546 * BitWidth : 1 547 * AccessType: RO 548 * ResetValue: (uint32_t)0x0 549 */ 550 SEDI_RBF_DEFINE(UART, MSR, RI, 6, 1, RO, (uint32_t)0x0); 551 SEDI_RBFV_DEFINE(UART, MSR, RI, ASSERTED, 0x1); 552 SEDI_RBFV_DEFINE(UART, MSR, RI, DEASSERTED, 0x0); 553 554 /* 555 * Bit Field of Register MSR 556 * DCD: 557 * BitOffset : 7 558 * BitWidth : 1 559 * AccessType: RO 560 * ResetValue: (uint32_t)0x0 561 */ 562 SEDI_RBF_DEFINE(UART, MSR, DCD, 7, 1, RO, (uint32_t)0x0); 563 SEDI_RBFV_DEFINE(UART, MSR, DCD, ASSERTED, 0x1); 564 SEDI_RBFV_DEFINE(UART, MSR, DCD, DEASSERTED, 0x0); 565 566 /* 567 * Bit Field of Register MSR 568 * RSVD_MSR_31to8: 569 * BitOffset : 8 570 * BitWidth : 24 571 * AccessType: RO 572 * ResetValue: (uint32_t)0x0 573 */ 574 SEDI_RBF_DEFINE(UART, MSR, RSVD_MSR_31to8, 8, 24, RO, (uint32_t)0x0); 575 576 /* ********* UART SCR *********** 577 * 578 * Register of SEDI UART 579 * SCR: Scratchpad Register 580 * AddressOffset : 0x1c 581 * AccessType : RW 582 * WritableBitMask: 0xff 583 * ResetValue : (uint32_t)0x0 584 */ 585 SEDI_REG_DEFINE(UART, SCR, 0x1c, RW, (uint32_t)0xff, (uint32_t)0x0); 586 587 /* 588 * Bit Field of Register SCR 589 * SCR: 590 * BitOffset : 0 591 * BitWidth : 8 592 * AccessType: RW 593 * ResetValue: (uint32_t)0x0 594 */ 595 SEDI_RBF_DEFINE(UART, SCR, SCR, 0, 8, RW, (uint32_t)0x0); 596 597 /* 598 * Bit Field of Register SCR 599 * RSVD_SCR_31to8: 600 * BitOffset : 8 601 * BitWidth : 24 602 * AccessType: RO 603 * ResetValue: (uint32_t)0x0 604 */ 605 SEDI_RBF_DEFINE(UART, SCR, RSVD_SCR_31to8, 8, 24, RO, (uint32_t)0x0); 606 607 /* ********* UART FAR *********** 608 * 609 * Register of SEDI UART 610 * FAR: FIFO Access Register 611 * AddressOffset : 0x70 612 * AccessType : RO 613 * WritableBitMask: 0x0 614 * ResetValue : (uint32_t)0x0 615 */ 616 SEDI_REG_DEFINE(UART, FAR, 0x70, RO, (uint32_t)0x0, (uint32_t)0x0); 617 618 /* 619 * Bit Field of Register FAR 620 * FAR: 621 * BitOffset : 0 622 * BitWidth : 1 623 * AccessType: RO 624 * ResetValue: (uint32_t)0x0 625 */ 626 SEDI_RBF_DEFINE(UART, FAR, FAR, 0, 1, RO, (uint32_t)0x0); 627 SEDI_RBFV_DEFINE(UART, FAR, FAR, DISABLED, 0x0); 628 SEDI_RBFV_DEFINE(UART, FAR, FAR, ENABLED, 0x1); 629 630 /* 631 * Bit Field of Register FAR 632 * RSVD_FAR_31to1: 633 * BitOffset : 1 634 * BitWidth : 31 635 * AccessType: RO 636 * ResetValue: (uint32_t)0x0 637 */ 638 SEDI_RBF_DEFINE(UART, FAR, RSVD_FAR_31to1, 1, 31, RO, (uint32_t)0x0); 639 640 /* ********* UART USR *********** 641 * 642 * Register of SEDI UART 643 * USR: UART Status register 644 * AddressOffset : 0x7c 645 * AccessType : RO 646 * WritableBitMask: 0x0 647 * ResetValue : (uint32_t)0x6 648 */ 649 SEDI_REG_DEFINE(UART, USR, 0x7c, RO, (uint32_t)0x0, (uint32_t)0x6); 650 651 /* 652 * Bit Field of Register USR 653 * RSVD_BUSY: 654 * BitOffset : 0 655 * BitWidth : 1 656 * AccessType: RO 657 * ResetValue: (uint32_t)0x0 658 */ 659 SEDI_RBF_DEFINE(UART, USR, RSVD_BUSY, 0, 1, RO, (uint32_t)0x0); 660 SEDI_RBFV_DEFINE(UART, USR, RSVD_BUSY, BUSY, 0x1); 661 SEDI_RBFV_DEFINE(UART, USR, RSVD_BUSY, IDLE, 0x0); 662 663 /* 664 * Bit Field of Register USR 665 * TFNF: 666 * BitOffset : 1 667 * BitWidth : 1 668 * AccessType: RO 669 * ResetValue: (uint32_t)0x1 670 */ 671 SEDI_RBF_DEFINE(UART, USR, TFNF, 1, 1, RO, (uint32_t)0x1); 672 SEDI_RBFV_DEFINE(UART, USR, TFNF, FULL, 0x0); 673 SEDI_RBFV_DEFINE(UART, USR, TFNF, NOT_FULL, 0x1); 674 675 /* 676 * Bit Field of Register USR 677 * TFE: 678 * BitOffset : 2 679 * BitWidth : 1 680 * AccessType: RO 681 * ResetValue: (uint32_t)0x1 682 */ 683 SEDI_RBF_DEFINE(UART, USR, TFE, 2, 1, RO, (uint32_t)0x1); 684 SEDI_RBFV_DEFINE(UART, USR, TFE, EMPTY, 0x1); 685 SEDI_RBFV_DEFINE(UART, USR, TFE, NOT_EMPTY, 0x0); 686 687 /* 688 * Bit Field of Register USR 689 * RFNE: 690 * BitOffset : 3 691 * BitWidth : 1 692 * AccessType: RO 693 * ResetValue: (uint32_t)0x0 694 */ 695 SEDI_RBF_DEFINE(UART, USR, RFNE, 3, 1, RO, (uint32_t)0x0); 696 SEDI_RBFV_DEFINE(UART, USR, RFNE, EMPTY, 0x0); 697 SEDI_RBFV_DEFINE(UART, USR, RFNE, NOT_EMPTY, 0x1); 698 699 /* 700 * Bit Field of Register USR 701 * RFF: 702 * BitOffset : 4 703 * BitWidth : 1 704 * AccessType: RO 705 * ResetValue: (uint32_t)0x0 706 */ 707 SEDI_RBF_DEFINE(UART, USR, RFF, 4, 1, RO, (uint32_t)0x0); 708 SEDI_RBFV_DEFINE(UART, USR, RFF, FULL, 0x1); 709 SEDI_RBFV_DEFINE(UART, USR, RFF, NOT_FULL, 0x0); 710 711 /* 712 * Bit Field of Register USR 713 * RSVD_USR_31to5: 714 * BitOffset : 5 715 * BitWidth : 27 716 * AccessType: RO 717 * ResetValue: (uint32_t)0x0 718 */ 719 SEDI_RBF_DEFINE(UART, USR, RSVD_USR_31to5, 5, 27, RO, (uint32_t)0x0); 720 721 /* ********* UART TFL *********** 722 * 723 * Register of SEDI UART 724 * TFL: Transmit FIFO Level 725 * AddressOffset : 0x80 726 * AccessType : RO 727 * WritableBitMask: 0x0 728 * ResetValue : (uint32_t)0x0 729 */ 730 SEDI_REG_DEFINE(UART, TFL, 0x80, RO, (uint32_t)0x0, (uint32_t)0x0); 731 732 /* 733 * Bit Field of Register TFL 734 * tfl: 735 * BitOffset : 0 736 * BitWidth : 7 737 * AccessType: RO 738 * ResetValue: (uint32_t)0x0 739 */ 740 SEDI_RBF_DEFINE(UART, TFL, tfl, 0, 7, RO, (uint32_t)0x0); 741 742 /* 743 * Bit Field of Register TFL 744 * RSVD_TFL_31toADDR_WIDTH: 745 * BitOffset : 7 746 * BitWidth : 25 747 * AccessType: RO 748 * ResetValue: (uint32_t)0x0 749 */ 750 SEDI_RBF_DEFINE(UART, TFL, RSVD_TFL_31toADDR_WIDTH, 7, 25, RO, (uint32_t)0x0); 751 752 /* ********* UART RFL *********** 753 * 754 * Register of SEDI UART 755 * RFL: Receive FIFO Level 756 * AddressOffset : 0x84 757 * AccessType : RO 758 * WritableBitMask: 0x0 759 * ResetValue : (uint32_t)0x0 760 */ 761 SEDI_REG_DEFINE(UART, RFL, 0x84, RO, (uint32_t)0x0, (uint32_t)0x0); 762 763 /* 764 * Bit Field of Register RFL 765 * rfl: 766 * BitOffset : 0 767 * BitWidth : 7 768 * AccessType: RO 769 * ResetValue: (uint32_t)0x0 770 */ 771 SEDI_RBF_DEFINE(UART, RFL, rfl, 0, 7, RO, (uint32_t)0x0); 772 773 /* 774 * Bit Field of Register RFL 775 * RSVD_RFL_31toADDR_WIDTH: 776 * BitOffset : 7 777 * BitWidth : 25 778 * AccessType: RO 779 * ResetValue: (uint32_t)0x0 780 */ 781 SEDI_RBF_DEFINE(UART, RFL, RSVD_RFL_31toADDR_WIDTH, 7, 25, RO, (uint32_t)0x0); 782 783 /* ********* UART HTX *********** 784 * 785 * Register of SEDI UART 786 * HTX: Halt TX 787 * AddressOffset : 0xa4 788 * AccessType : RW 789 * WritableBitMask: 0x1 790 * ResetValue : (uint32_t)0x0 791 */ 792 SEDI_REG_DEFINE(UART, HTX, 0xa4, RW, (uint32_t)0x1, (uint32_t)0x0); 793 794 /* 795 * Bit Field of Register HTX 796 * HTX: 797 * BitOffset : 0 798 * BitWidth : 1 799 * AccessType: RW 800 * ResetValue: (uint32_t)0x0 801 */ 802 SEDI_RBF_DEFINE(UART, HTX, HTX, 0, 1, RW, (uint32_t)0x0); 803 SEDI_RBFV_DEFINE(UART, HTX, HTX, DISABLED, 0x0); 804 SEDI_RBFV_DEFINE(UART, HTX, HTX, ENABLED, 0x1); 805 806 /* 807 * Bit Field of Register HTX 808 * RSVD_HTX_31to1: 809 * BitOffset : 1 810 * BitWidth : 31 811 * AccessType: RO 812 * ResetValue: (uint32_t)0x0 813 */ 814 SEDI_RBF_DEFINE(UART, HTX, RSVD_HTX_31to1, 1, 31, RO, (uint32_t)0x0); 815 816 /* ********* UART DMASA *********** 817 * 818 * Register of SEDI UART 819 * DMASA: DMA Software Acknowledge Register 820 * AddressOffset : 0xa8 821 * AccessType : RW 822 * WritableBitMask: 0x1 823 * ResetValue : (uint32_t)0x0 824 */ 825 SEDI_REG_DEFINE(UART, DMASA, 0xa8, RW, (uint32_t)0x1, (uint32_t)0x0); 826 827 /* 828 * Bit Field of Register DMASA 829 * DMASA: 830 * BitOffset : 0 831 * BitWidth : 1 832 * AccessType: RW 833 * ResetValue: (uint32_t)0x0 834 */ 835 SEDI_RBF_DEFINE(UART, DMASA, DMASA, 0, 1, RW, (uint32_t)0x0); 836 SEDI_RBFV_DEFINE(UART, DMASA, DMASA, SOFT_ACK, 0x1); 837 838 /* 839 * Bit Field of Register DMASA 840 * RSVD_DMASA_31to1: 841 * BitOffset : 1 842 * BitWidth : 31 843 * AccessType: RO 844 * ResetValue: (uint32_t)0x0 845 */ 846 SEDI_RBF_DEFINE(UART, DMASA, RSVD_DMASA_31to1, 1, 31, RO, (uint32_t)0x0); 847 848 /* ********* UART TCR *********** 849 * 850 * Register of SEDI UART 851 * TCR: Transceiver Control Register 852 * AddressOffset : 0xac 853 * AccessType : RW 854 * WritableBitMask: 0x1f 855 * ResetValue : (uint32_t)0x6 856 */ 857 SEDI_REG_DEFINE(UART, TCR, 0xac, RW, (uint32_t)0x1f, (uint32_t)0x6); 858 859 /* 860 * Bit Field of Register TCR 861 * RS485_EN: 862 * BitOffset : 0 863 * BitWidth : 1 864 * AccessType: RW 865 * ResetValue: (uint32_t)0x0 866 */ 867 SEDI_RBF_DEFINE(UART, TCR, RS485_EN, 0, 1, RW, (uint32_t)0x0); 868 SEDI_RBFV_DEFINE(UART, TCR, RS485_EN, 0, 0); 869 SEDI_RBFV_DEFINE(UART, TCR, RS485_EN, 1, 1); 870 871 /* 872 * Bit Field of Register TCR 873 * RE_POL: 874 * BitOffset : 1 875 * BitWidth : 1 876 * AccessType: RW 877 * ResetValue: (uint32_t)0x1 878 */ 879 SEDI_RBF_DEFINE(UART, TCR, RE_POL, 1, 1, RW, (uint32_t)0x1); 880 SEDI_RBFV_DEFINE(UART, TCR, RE_POL, 0, 0); 881 SEDI_RBFV_DEFINE(UART, TCR, RE_POL, 1, 1); 882 883 /* 884 * Bit Field of Register TCR 885 * DE_POL: 886 * BitOffset : 2 887 * BitWidth : 1 888 * AccessType: RW 889 * ResetValue: (uint32_t)0x1 890 */ 891 SEDI_RBF_DEFINE(UART, TCR, DE_POL, 2, 1, RW, (uint32_t)0x1); 892 SEDI_RBFV_DEFINE(UART, TCR, DE_POL, 0, 0); 893 SEDI_RBFV_DEFINE(UART, TCR, DE_POL, 1, 1); 894 895 /* 896 * Bit Field of Register TCR 897 * XFER_MODE: 898 * BitOffset : 3 899 * BitWidth : 2 900 * AccessType: RW 901 * ResetValue: (uint32_t)0x0 902 */ 903 SEDI_RBF_DEFINE(UART, TCR, XFER_MODE, 3, 2, RW, (uint32_t)0x0); 904 905 /* 906 * Bit Field of Register TCR 907 * RSVD_TCR_31to5: 908 * BitOffset : 5 909 * BitWidth : 27 910 * AccessType: RO 911 * ResetValue: (uint32_t)0x0 912 */ 913 SEDI_RBF_DEFINE(UART, TCR, RSVD_TCR_31to5, 5, 27, RO, (uint32_t)0x0); 914 915 /* ********* UART DE_EN *********** 916 * 917 * Register of SEDI UART 918 * DE_EN: Driver Output Enable Register 919 * AddressOffset : 0xb0 920 * AccessType : RW 921 * WritableBitMask: 0x1 922 * ResetValue : (uint32_t)0x0 923 */ 924 SEDI_REG_DEFINE(UART, DE_EN, 0xb0, RW, (uint32_t)0x1, (uint32_t)0x0); 925 926 /* 927 * Bit Field of Register DE_EN 928 * DE_Enable: 929 * BitOffset : 0 930 * BitWidth : 1 931 * AccessType: RW 932 * ResetValue: (uint32_t)0x0 933 */ 934 SEDI_RBF_DEFINE(UART, DE_EN, DE_Enable, 0, 1, RW, (uint32_t)0x0); 935 SEDI_RBFV_DEFINE(UART, DE_EN, DE_Enable, 0, 0); 936 SEDI_RBFV_DEFINE(UART, DE_EN, DE_Enable, 1, 1); 937 938 /* 939 * Bit Field of Register DE_EN 940 * RSVD_DE_EN_31to1: 941 * BitOffset : 1 942 * BitWidth : 31 943 * AccessType: RO 944 * ResetValue: (uint32_t)0x0 945 */ 946 SEDI_RBF_DEFINE(UART, DE_EN, RSVD_DE_EN_31to1, 1, 31, RO, (uint32_t)0x0); 947 948 /* ********* UART RE_EN *********** 949 * 950 * Register of SEDI UART 951 * RE_EN: Receiver Output Enable Register 952 * AddressOffset : 0xb4 953 * AccessType : RW 954 * WritableBitMask: 0x1 955 * ResetValue : (uint32_t)0x0 956 */ 957 SEDI_REG_DEFINE(UART, RE_EN, 0xb4, RW, (uint32_t)0x1, (uint32_t)0x0); 958 959 /* 960 * Bit Field of Register RE_EN 961 * RE_Enable: 962 * BitOffset : 0 963 * BitWidth : 1 964 * AccessType: RW 965 * ResetValue: (uint32_t)0x0 966 */ 967 SEDI_RBF_DEFINE(UART, RE_EN, RE_Enable, 0, 1, RW, (uint32_t)0x0); 968 SEDI_RBFV_DEFINE(UART, RE_EN, RE_Enable, 0, 0); 969 SEDI_RBFV_DEFINE(UART, RE_EN, RE_Enable, 1, 1); 970 971 /* 972 * Bit Field of Register RE_EN 973 * RSVD_RE_EN_31to1: 974 * BitOffset : 1 975 * BitWidth : 31 976 * AccessType: RO 977 * ResetValue: (uint32_t)0x0 978 */ 979 SEDI_RBF_DEFINE(UART, RE_EN, RSVD_RE_EN_31to1, 1, 31, RO, (uint32_t)0x0); 980 981 /* ********* UART DET *********** 982 * 983 * Register of SEDI UART 984 * DET: Driver Output Enable Timing Register 985 * AddressOffset : 0xb8 986 * AccessType : RW 987 * WritableBitMask: 0xff00ff 988 * ResetValue : (uint32_t)0x0 989 */ 990 SEDI_REG_DEFINE(UART, DET, 0xb8, RW, (uint32_t)0xff00ff, (uint32_t)0x0); 991 992 /* 993 * Bit Field of Register DET 994 * DE_Assertion_Time: 995 * BitOffset : 0 996 * BitWidth : 8 997 * AccessType: RW 998 * ResetValue: (uint32_t)0x0 999 */ 1000 SEDI_RBF_DEFINE(UART, DET, DE_Assertion_Time, 0, 8, RW, (uint32_t)0x0); 1001 1002 /* 1003 * Bit Field of Register DET 1004 * RSVD_DE_AT_15to8: 1005 * BitOffset : 8 1006 * BitWidth : 8 1007 * AccessType: RO 1008 * ResetValue: (uint32_t)0x0 1009 */ 1010 SEDI_RBF_DEFINE(UART, DET, RSVD_DE_AT_15to8, 8, 8, RO, (uint32_t)0x0); 1011 1012 /* 1013 * Bit Field of Register DET 1014 * DE_De_assertion_Time: 1015 * BitOffset : 16 1016 * BitWidth : 8 1017 * AccessType: RW 1018 * ResetValue: (uint32_t)0x0 1019 */ 1020 SEDI_RBF_DEFINE(UART, DET, DE_De_assertion_Time, 16, 8, RW, (uint32_t)0x0); 1021 1022 /* 1023 * Bit Field of Register DET 1024 * RSVD_DE_DEAT_31to24: 1025 * BitOffset : 24 1026 * BitWidth : 8 1027 * AccessType: RO 1028 * ResetValue: (uint32_t)0x0 1029 */ 1030 SEDI_RBF_DEFINE(UART, DET, RSVD_DE_DEAT_31to24, 24, 8, RO, (uint32_t)0x0); 1031 1032 /* ********* UART TAT *********** 1033 * 1034 * Register of SEDI UART 1035 * TAT: TurnAround Timing Register 1036 * AddressOffset : 0xbc 1037 * AccessType : RW 1038 * WritableBitMask: 0xffffffff 1039 * ResetValue : (uint32_t)0x0 1040 */ 1041 SEDI_REG_DEFINE(UART, TAT, 0xbc, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 1042 1043 /* 1044 * Bit Field of Register TAT 1045 * DE_to_RE: 1046 * BitOffset : 0 1047 * BitWidth : 16 1048 * AccessType: RW 1049 * ResetValue: (uint32_t)0x0 1050 */ 1051 SEDI_RBF_DEFINE(UART, TAT, DE_to_RE, 0, 16, RW, (uint32_t)0x0); 1052 1053 /* 1054 * Bit Field of Register TAT 1055 * RE_to_DE: 1056 * BitOffset : 16 1057 * BitWidth : 16 1058 * AccessType: RW 1059 * ResetValue: (uint32_t)0x0 1060 */ 1061 SEDI_RBF_DEFINE(UART, TAT, RE_to_DE, 16, 16, RW, (uint32_t)0x0); 1062 1063 /* ********* UART DLF *********** 1064 * 1065 * Register of SEDI UART 1066 * DLF: Divisor Latch Fraction Register 1067 * AddressOffset : 0xc0 1068 * AccessType : RW 1069 * WritableBitMask: 0xf 1070 * ResetValue : (uint32_t)0x0 1071 */ 1072 SEDI_REG_DEFINE(UART, DLF, 0xc0, RW, (uint32_t)0xf, (uint32_t)0x0); 1073 1074 /* 1075 * Bit Field of Register DLF 1076 * DLF: 1077 * BitOffset : 0 1078 * BitWidth : 4 1079 * AccessType: RW 1080 * ResetValue: (uint32_t)0x0 1081 */ 1082 SEDI_RBF_DEFINE(UART, DLF, DLF, 0, 4, RW, (uint32_t)0x0); 1083 1084 /* 1085 * Bit Field of Register DLF 1086 * RSVD_DLF: 1087 * BitOffset : 4 1088 * BitWidth : 28 1089 * AccessType: RO 1090 * ResetValue: (uint32_t)0x0 1091 */ 1092 SEDI_RBF_DEFINE(UART, DLF, RSVD_DLF, 4, 28, RO, (uint32_t)0x0); 1093 1094 /* ********* UART RAR *********** 1095 * 1096 * Register of SEDI UART 1097 * RAR: Receive Address Register 1098 * AddressOffset : 0xc4 1099 * AccessType : RW 1100 * WritableBitMask: 0xff 1101 * ResetValue : (uint32_t)0x0 1102 */ 1103 SEDI_REG_DEFINE(UART, RAR, 0xc4, RW, (uint32_t)0xff, (uint32_t)0x0); 1104 1105 /* 1106 * Bit Field of Register RAR 1107 * RAR: 1108 * BitOffset : 0 1109 * BitWidth : 8 1110 * AccessType: RW 1111 * ResetValue: (uint32_t)0x0 1112 */ 1113 SEDI_RBF_DEFINE(UART, RAR, RAR, 0, 8, RW, (uint32_t)0x0); 1114 1115 /* 1116 * Bit Field of Register RAR 1117 * RSVD_RAR_31to8: 1118 * BitOffset : 8 1119 * BitWidth : 24 1120 * AccessType: RO 1121 * ResetValue: (uint32_t)0x0 1122 */ 1123 SEDI_RBF_DEFINE(UART, RAR, RSVD_RAR_31to8, 8, 24, RO, (uint32_t)0x0); 1124 1125 /* ********* UART TAR *********** 1126 * 1127 * Register of SEDI UART 1128 * TAR: Transmit Address Register 1129 * AddressOffset : 0xc8 1130 * AccessType : RW 1131 * WritableBitMask: 0xff 1132 * ResetValue : (uint32_t)0x0 1133 */ 1134 SEDI_REG_DEFINE(UART, TAR, 0xc8, RW, (uint32_t)0xff, (uint32_t)0x0); 1135 1136 /* 1137 * Bit Field of Register TAR 1138 * TAR: 1139 * BitOffset : 0 1140 * BitWidth : 8 1141 * AccessType: RW 1142 * ResetValue: (uint32_t)0x0 1143 */ 1144 SEDI_RBF_DEFINE(UART, TAR, TAR, 0, 8, RW, (uint32_t)0x0); 1145 1146 /* 1147 * Bit Field of Register TAR 1148 * RSVD_TAR_31to8: 1149 * BitOffset : 8 1150 * BitWidth : 24 1151 * AccessType: RO 1152 * ResetValue: (uint32_t)0x0 1153 */ 1154 SEDI_RBF_DEFINE(UART, TAR, RSVD_TAR_31to8, 8, 24, RO, (uint32_t)0x0); 1155 1156 /* ********* UART LCR_EXT *********** 1157 * 1158 * Register of SEDI UART 1159 * LCR_EXT: Line Extended Control Register 1160 * AddressOffset : 0xcc 1161 * AccessType : RW 1162 * WritableBitMask: 0xf 1163 * ResetValue : (uint32_t)0x0 1164 */ 1165 SEDI_REG_DEFINE(UART, LCR_EXT, 0xcc, RW, (uint32_t)0xf, (uint32_t)0x0); 1166 1167 /* 1168 * Bit Field of Register LCR_EXT 1169 * DLS_E: 1170 * BitOffset : 0 1171 * BitWidth : 1 1172 * AccessType: RW 1173 * ResetValue: (uint32_t)0x0 1174 */ 1175 SEDI_RBF_DEFINE(UART, LCR_EXT, DLS_E, 0, 1, RW, (uint32_t)0x0); 1176 SEDI_RBFV_DEFINE(UART, LCR_EXT, DLS_E, 0, 0); 1177 SEDI_RBFV_DEFINE(UART, LCR_EXT, DLS_E, 1, 1); 1178 1179 /* 1180 * Bit Field of Register LCR_EXT 1181 * ADDR_MATCH: 1182 * BitOffset : 1 1183 * BitWidth : 1 1184 * AccessType: RW 1185 * ResetValue: (uint32_t)0x0 1186 */ 1187 SEDI_RBF_DEFINE(UART, LCR_EXT, ADDR_MATCH, 1, 1, RW, (uint32_t)0x0); 1188 SEDI_RBFV_DEFINE(UART, LCR_EXT, ADDR_MATCH, 0, 0); 1189 SEDI_RBFV_DEFINE(UART, LCR_EXT, ADDR_MATCH, 1, 1); 1190 1191 /* 1192 * Bit Field of Register LCR_EXT 1193 * SEND_ADDR: 1194 * BitOffset : 2 1195 * BitWidth : 1 1196 * AccessType: RW 1197 * ResetValue: (uint32_t)0x0 1198 */ 1199 SEDI_RBF_DEFINE(UART, LCR_EXT, SEND_ADDR, 2, 1, RW, (uint32_t)0x0); 1200 SEDI_RBFV_DEFINE(UART, LCR_EXT, SEND_ADDR, 0, 0); 1201 SEDI_RBFV_DEFINE(UART, LCR_EXT, SEND_ADDR, 1, 1); 1202 1203 /* 1204 * Bit Field of Register LCR_EXT 1205 * TRANSMIT_MODE: 1206 * BitOffset : 3 1207 * BitWidth : 1 1208 * AccessType: RW 1209 * ResetValue: (uint32_t)0x0 1210 */ 1211 SEDI_RBF_DEFINE(UART, LCR_EXT, TRANSMIT_MODE, 3, 1, RW, (uint32_t)0x0); 1212 SEDI_RBFV_DEFINE(UART, LCR_EXT, TRANSMIT_MODE, 0, 0); 1213 SEDI_RBFV_DEFINE(UART, LCR_EXT, TRANSMIT_MODE, 1, 1); 1214 1215 /* 1216 * Bit Field of Register LCR_EXT 1217 * RSVD_LCR_EXT: 1218 * BitOffset : 4 1219 * BitWidth : 28 1220 * AccessType: RO 1221 * ResetValue: (uint32_t)0x0 1222 */ 1223 SEDI_RBF_DEFINE(UART, LCR_EXT, RSVD_LCR_EXT, 4, 28, RO, (uint32_t)0x0); 1224 1225 /* ********* UART CPR *********** 1226 * 1227 * Register of SEDI UART 1228 * CPR: Component Parameter Register 1229 * AddressOffset : 0xf4 1230 * AccessType : RO 1231 * WritableBitMask: 0x0 1232 * ResetValue : (uint32_t)0x43532 1233 */ 1234 SEDI_REG_DEFINE(UART, CPR, 0xf4, RO, (uint32_t)0x0, (uint32_t)0x43532); 1235 1236 /* 1237 * Bit Field of Register CPR 1238 * APB_DATA_WIDTH: 1239 * BitOffset : 0 1240 * BitWidth : 2 1241 * AccessType: RO 1242 * ResetValue: (uint32_t)0x2 1243 */ 1244 SEDI_RBF_DEFINE(UART, CPR, APB_DATA_WIDTH, 0, 2, RO, (uint32_t)0x2); 1245 SEDI_RBFV_DEFINE(UART, CPR, APB_DATA_WIDTH, APB_16BITS, 0x1); 1246 SEDI_RBFV_DEFINE(UART, CPR, APB_DATA_WIDTH, APB_32BITS, 0x2); 1247 SEDI_RBFV_DEFINE(UART, CPR, APB_DATA_WIDTH, APB_8BITS, 0x0); 1248 1249 /* 1250 * Bit Field of Register CPR 1251 * RSVD_CPR_3to2: 1252 * BitOffset : 2 1253 * BitWidth : 2 1254 * AccessType: RO 1255 * ResetValue: (uint32_t)0x0 1256 */ 1257 SEDI_RBF_DEFINE(UART, CPR, RSVD_CPR_3to2, 2, 2, RO, (uint32_t)0x0); 1258 1259 /* 1260 * Bit Field of Register CPR 1261 * AFCE_MODE: 1262 * BitOffset : 4 1263 * BitWidth : 1 1264 * AccessType: RO 1265 * ResetValue: (uint32_t)0x1 1266 */ 1267 SEDI_RBF_DEFINE(UART, CPR, AFCE_MODE, 4, 1, RO, (uint32_t)0x1); 1268 SEDI_RBFV_DEFINE(UART, CPR, AFCE_MODE, DISABLED, 0x0); 1269 SEDI_RBFV_DEFINE(UART, CPR, AFCE_MODE, ENABLED, 0x1); 1270 1271 /* 1272 * Bit Field of Register CPR 1273 * THRE_MODE: 1274 * BitOffset : 5 1275 * BitWidth : 1 1276 * AccessType: RO 1277 * ResetValue: (uint32_t)0x1 1278 */ 1279 SEDI_RBF_DEFINE(UART, CPR, THRE_MODE, 5, 1, RO, (uint32_t)0x1); 1280 SEDI_RBFV_DEFINE(UART, CPR, THRE_MODE, DISABLED, 0x0); 1281 SEDI_RBFV_DEFINE(UART, CPR, THRE_MODE, ENABLED, 0x1); 1282 1283 /* 1284 * Bit Field of Register CPR 1285 * SIR_MODE: 1286 * BitOffset : 6 1287 * BitWidth : 1 1288 * AccessType: RO 1289 * ResetValue: (uint32_t)0x0 1290 */ 1291 SEDI_RBF_DEFINE(UART, CPR, SIR_MODE, 6, 1, RO, (uint32_t)0x0); 1292 SEDI_RBFV_DEFINE(UART, CPR, SIR_MODE, DISABLED, 0x0); 1293 SEDI_RBFV_DEFINE(UART, CPR, SIR_MODE, ENABLED, 0x1); 1294 1295 /* 1296 * Bit Field of Register CPR 1297 * SIR_LP_MODE: 1298 * BitOffset : 7 1299 * BitWidth : 1 1300 * AccessType: RO 1301 * ResetValue: (uint32_t)0x0 1302 */ 1303 SEDI_RBF_DEFINE(UART, CPR, SIR_LP_MODE, 7, 1, RO, (uint32_t)0x0); 1304 SEDI_RBFV_DEFINE(UART, CPR, SIR_LP_MODE, DISABLED, 0x0); 1305 SEDI_RBFV_DEFINE(UART, CPR, SIR_LP_MODE, ENABLED, 0x1); 1306 1307 /* 1308 * Bit Field of Register CPR 1309 * ADDITIONAL_FEAT: 1310 * BitOffset : 8 1311 * BitWidth : 1 1312 * AccessType: RO 1313 * ResetValue: (uint32_t)0x1 1314 */ 1315 SEDI_RBF_DEFINE(UART, CPR, ADDITIONAL_FEAT, 8, 1, RO, (uint32_t)0x1); 1316 SEDI_RBFV_DEFINE(UART, CPR, ADDITIONAL_FEAT, DISABLED, 0x0); 1317 SEDI_RBFV_DEFINE(UART, CPR, ADDITIONAL_FEAT, ENABLED, 0x1); 1318 1319 /* 1320 * Bit Field of Register CPR 1321 * FIFO_ACCESS: 1322 * BitOffset : 9 1323 * BitWidth : 1 1324 * AccessType: RO 1325 * ResetValue: (uint32_t)0x0 1326 */ 1327 SEDI_RBF_DEFINE(UART, CPR, FIFO_ACCESS, 9, 1, RO, (uint32_t)0x0); 1328 SEDI_RBFV_DEFINE(UART, CPR, FIFO_ACCESS, DISABLED, 0x0); 1329 SEDI_RBFV_DEFINE(UART, CPR, FIFO_ACCESS, ENABLED, 0x1); 1330 1331 /* 1332 * Bit Field of Register CPR 1333 * FIFO_STAT: 1334 * BitOffset : 10 1335 * BitWidth : 1 1336 * AccessType: RO 1337 * ResetValue: (uint32_t)0x1 1338 */ 1339 SEDI_RBF_DEFINE(UART, CPR, FIFO_STAT, 10, 1, RO, (uint32_t)0x1); 1340 SEDI_RBFV_DEFINE(UART, CPR, FIFO_STAT, DISABLED, 0x0); 1341 SEDI_RBFV_DEFINE(UART, CPR, FIFO_STAT, ENABLED, 0x1); 1342 1343 /* 1344 * Bit Field of Register CPR 1345 * SHADOW: 1346 * BitOffset : 11 1347 * BitWidth : 1 1348 * AccessType: RO 1349 * ResetValue: (uint32_t)0x0 1350 */ 1351 SEDI_RBF_DEFINE(UART, CPR, SHADOW, 11, 1, RO, (uint32_t)0x0); 1352 SEDI_RBFV_DEFINE(UART, CPR, SHADOW, DISABLED, 0x0); 1353 SEDI_RBFV_DEFINE(UART, CPR, SHADOW, ENABLED, 0x1); 1354 1355 /* 1356 * Bit Field of Register CPR 1357 * UART_ADD_ENCODED_PARAMS: 1358 * BitOffset : 12 1359 * BitWidth : 1 1360 * AccessType: RO 1361 * ResetValue: (uint32_t)0x1 1362 */ 1363 SEDI_RBF_DEFINE(UART, CPR, UART_ADD_ENCODED_PARAMS, 12, 1, RO, (uint32_t)0x1); 1364 SEDI_RBFV_DEFINE(UART, CPR, UART_ADD_ENCODED_PARAMS, DISABLED, 0x0); 1365 SEDI_RBFV_DEFINE(UART, CPR, UART_ADD_ENCODED_PARAMS, ENABLED, 0x1); 1366 1367 /* 1368 * Bit Field of Register CPR 1369 * DMA_EXTRA: 1370 * BitOffset : 13 1371 * BitWidth : 1 1372 * AccessType: RO 1373 * ResetValue: (uint32_t)0x1 1374 */ 1375 SEDI_RBF_DEFINE(UART, CPR, DMA_EXTRA, 13, 1, RO, (uint32_t)0x1); 1376 SEDI_RBFV_DEFINE(UART, CPR, DMA_EXTRA, DISABLED, 0x0); 1377 SEDI_RBFV_DEFINE(UART, CPR, DMA_EXTRA, ENABLED, 0x1); 1378 1379 /* 1380 * Bit Field of Register CPR 1381 * RSVD_CPR_15to14: 1382 * BitOffset : 14 1383 * BitWidth : 2 1384 * AccessType: RO 1385 * ResetValue: (uint32_t)0x0 1386 */ 1387 SEDI_RBF_DEFINE(UART, CPR, RSVD_CPR_15to14, 14, 2, RO, (uint32_t)0x0); 1388 1389 /* 1390 * Bit Field of Register CPR 1391 * FIFO_MODE: 1392 * BitOffset : 16 1393 * BitWidth : 8 1394 * AccessType: RO 1395 * ResetValue: (uint32_t)0x4 1396 */ 1397 SEDI_RBF_DEFINE(UART, CPR, FIFO_MODE, 16, 8, RO, (uint32_t)0x4); 1398 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_0, 0x0); 1399 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_1024, 0x40); 1400 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_128, 0x8); 1401 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_16, 0x1); 1402 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_2048, 0x80); 1403 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_256, 0x10); 1404 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_32, 0x2); 1405 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_512, 0x20); 1406 SEDI_RBFV_DEFINE(UART, CPR, FIFO_MODE, FIFO_MODE_64, 0x4); 1407 1408 /* 1409 * Bit Field of Register CPR 1410 * RSVD_CPR_31to24: 1411 * BitOffset : 24 1412 * BitWidth : 8 1413 * AccessType: RO 1414 * ResetValue: (uint32_t)0x0 1415 */ 1416 SEDI_RBF_DEFINE(UART, CPR, RSVD_CPR_31to24, 24, 8, RO, (uint32_t)0x0); 1417 1418 /* ********* UART UCV *********** 1419 * 1420 * Register of SEDI UART 1421 * UCV: UART Component Version 1422 * AddressOffset : 0xf8 1423 * AccessType : RO 1424 * WritableBitMask: 0x0 1425 * ResetValue : (uint32_t)0x3430322a 1426 */ 1427 SEDI_REG_DEFINE(UART, UCV, 0xf8, RO, (uint32_t)0x0, (uint32_t)0x3430322a); 1428 1429 /* 1430 * Bit Field of Register UCV 1431 * UART_Component_Version: 1432 * BitOffset : 0 1433 * BitWidth : 32 1434 * AccessType: RO 1435 * ResetValue: (uint32_t)0x3430322a 1436 */ 1437 SEDI_RBF_DEFINE(UART, UCV, UART_Component_Version, 0, 32, RO, (uint32_t)0x3430322a); 1438 1439 /* ********* UART CTR *********** 1440 * 1441 * Register of SEDI UART 1442 * CTR: Component Type Register 1443 * AddressOffset : 0xfc 1444 * AccessType : RO 1445 * WritableBitMask: 0x0 1446 * ResetValue : (uint32_t)0x44570110 1447 */ 1448 SEDI_REG_DEFINE(UART, CTR, 0xfc, RO, (uint32_t)0x0, (uint32_t)0x44570110); 1449 1450 /* 1451 * Bit Field of Register CTR 1452 * Peripheral_ID: 1453 * BitOffset : 0 1454 * BitWidth : 32 1455 * AccessType: RO 1456 * ResetValue: (uint32_t)0x44570110 1457 */ 1458 SEDI_RBF_DEFINE(UART, CTR, Peripheral_ID, 0, 32, RO, (uint32_t)0x44570110); 1459 1460 /* 1461 * Registers' Address Map Structure 1462 */ 1463 1464 typedef struct { 1465 /* Rx Buffer/ Tx Holding/ Div Latch Low register */ 1466 __IO_RW uint32_t rbr_thr_dll; 1467 1468 /* Interrupt Enable / Div Latch High register */ 1469 __IO_RW uint32_t ier_dlh; 1470 1471 /* Interrupt Identification/FIFO Ctrl register */ 1472 __IO_RW uint32_t iir_fcr; 1473 1474 /* Line Control Register */ 1475 __IO_RW uint32_t lcr; 1476 1477 /* Modem Control Register */ 1478 __IO_RW uint32_t mcr; 1479 1480 /* Line Status Register */ 1481 __IO_R uint32_t lsr; 1482 1483 /* Modem Status Register */ 1484 __IO_R uint32_t msr; 1485 1486 /* Scratchpad Register */ 1487 __IO_RW uint32_t scr; 1488 1489 /* Reserved */ 1490 __IO_RW uint32_t reserved0[20]; 1491 1492 /* FIFO Access Register */ 1493 __IO_R uint32_t far; 1494 1495 /* Reserved */ 1496 __IO_RW uint32_t reserved1[2]; 1497 1498 /* UART Status register */ 1499 __IO_R uint32_t usr; 1500 1501 /* Transmit FIFO Level */ 1502 __IO_R uint32_t tfl; 1503 1504 /* Receive FIFO Level */ 1505 __IO_R uint32_t rfl; 1506 1507 /* Reserved */ 1508 __IO_RW uint32_t reserved2[7]; 1509 1510 /* Halt TX */ 1511 __IO_RW uint32_t htx; 1512 1513 /* DMA Software Acknowledge Register */ 1514 __IO_RW uint32_t dmasa; 1515 1516 /* Transceiver Control Register */ 1517 __IO_RW uint32_t tcr; 1518 1519 /* Driver Output Enable Register */ 1520 __IO_RW uint32_t de_en; 1521 1522 /* Receiver Output Enable Register */ 1523 __IO_RW uint32_t re_en; 1524 1525 /* Driver Output Enable Timing Register */ 1526 __IO_RW uint32_t det; 1527 1528 /* TurnAround Timing Register */ 1529 __IO_RW uint32_t tat; 1530 1531 /* Divisor Latch Fraction Register */ 1532 __IO_RW uint32_t dlf; 1533 1534 /* Receive Address Register */ 1535 __IO_RW uint32_t rar; 1536 1537 /* Transmit Address Register */ 1538 __IO_RW uint32_t tar; 1539 1540 /* Line Extended Control Register */ 1541 __IO_RW uint32_t lcr_ext; 1542 1543 /* Reserved */ 1544 __IO_RW uint32_t reserved3[9]; 1545 1546 /* Component Parameter Register */ 1547 __IO_R uint32_t cpr; 1548 1549 /* UART Component Version */ 1550 __IO_R uint32_t ucv; 1551 1552 /* Component Type Register */ 1553 __IO_R uint32_t ctr; 1554 1555 } sedi_uart_regs_t; 1556 1557 1558 #endif /* _SEDI_UART_REGS_H_ */ 1559
