1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SECURITY_ENGINE_H 9 #define SECURITY_ENGINE_H 10 11 /******************************************************************************* 12 * Structure definition 13 ******************************************************************************/ 14 15 /* Security Engine Linked List */ 16 struct tegra_se_ll { 17 /* DMA buffer address */ 18 uint32_t addr; 19 /* Data length in DMA buffer */ 20 uint32_t data_len; 21 }; 22 23 #define SE_LL_MAX_BUFFER_NUM 4 24 typedef struct tegra_se_io_lst { 25 volatile uint32_t last_buff_num; 26 volatile struct tegra_se_ll buffer[SE_LL_MAX_BUFFER_NUM]; 27 } tegra_se_io_lst_t __attribute__((aligned(4))); 28 29 /* SE device structure */ 30 typedef struct tegra_se_dev { 31 /* Security Engine ID */ 32 const int se_num; 33 /* SE base address */ 34 const uint64_t se_base; 35 /* SE context size in AES blocks */ 36 const uint32_t ctx_size_blks; 37 /* pointer to source linked list buffer */ 38 tegra_se_io_lst_t *src_ll_buf; 39 /* pointer to destination linked list buffer */ 40 tegra_se_io_lst_t *dst_ll_buf; 41 /* LP context buffer pointer */ 42 uint32_t *ctx_save_buf; 43 } tegra_se_dev_t; 44 45 /* PKA1 device structure */ 46 typedef struct tegra_pka_dev { 47 /* PKA1 base address */ 48 uint64_t pka_base; 49 } tegra_pka_dev_t; 50 51 /******************************************************************************* 52 * Public interface 53 ******************************************************************************/ 54 void tegra_se_init(void); 55 int tegra_se_suspend(void); 56 void tegra_se_resume(void); 57 int tegra_se_save_tzram(void); 58 int32_t tegra_se_save_sha256_hash(uint64_t bl31_base, uint32_t src_len_inbyte); 59 60 #endif /* SECURITY_ENGINE_H */ 61
