1 /*
2 * Copyright (c) 2018 omSquare s.r.o.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT atmel_sam0_rtc
8
9 /**
10 * @file
11 * @brief Atmel SAM0 series RTC-based system timer
12 *
13 * This system timer implementation supports both tickless and ticking modes.
14 * In tickless mode, RTC counts continually in 32-bit mode and timeouts are
15 * scheduled using the RTC comparator. In ticking mode, RTC is configured to
16 * generate an interrupt every tick.
17 */
18
19 #include <zephyr/init.h>
20 #include <soc.h>
21 #include <zephyr/drivers/clock_control.h>
22 #include <zephyr/drivers/timer/system_timer.h>
23 #include <zephyr/drivers/pinctrl.h>
24 #include <zephyr/sys_clock.h>
25 #include <zephyr/irq.h>
26 #include <zephyr/sys/util.h>
27
28 /* RTC registers. */
29 #define RTC0 ((RtcMode0 *) DT_INST_REG_ADDR(0))
30
31 #ifdef MCLK
32 #define RTC_CLOCK_HW_CYCLES_PER_SEC SOC_ATMEL_SAM0_OSC32K_FREQ_HZ
33 #else
34 #define RTC_CLOCK_HW_CYCLES_PER_SEC SOC_ATMEL_SAM0_GCLK0_FREQ_HZ
35 #endif
36
37 /* Number of sys timer cycles per on tick. */
38 #define CYCLES_PER_TICK (RTC_CLOCK_HW_CYCLES_PER_SEC \
39 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
40
41 /* Maximum number of ticks. */
42 #define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
43
44 #ifdef CONFIG_TICKLESS_KERNEL
45
46 /*
47 * Due to the nature of clock synchronization, reading from or writing to some
48 * RTC registers takes approximately six RTC_GCLK cycles. This constant defines
49 * a safe threshold for the comparator.
50 */
51 #define TICK_THRESHOLD 7
52
53 BUILD_ASSERT(CYCLES_PER_TICK > TICK_THRESHOLD,
54 "CYCLES_PER_TICK must be greater than TICK_THRESHOLD for "
55 "tickless mode");
56
57 #else /* !CONFIG_TICKLESS_KERNEL */
58
59 /*
60 * For some reason, RTC does not generate interrupts when COMP == 0,
61 * MATCHCLR == 1 and PRESCALER == 0. So we need to check that CYCLES_PER_TICK
62 * is more than one.
63 */
64 BUILD_ASSERT(CYCLES_PER_TICK > 1,
65 "CYCLES_PER_TICK must be greater than 1 for ticking mode");
66
67 #endif /* CONFIG_TICKLESS_KERNEL */
68
69 /* Helper macro to get the correct GCLK GEN based on configuration. */
70 #define GCLK_GEN(n) GCLK_EVAL(n)
71 #define GCLK_EVAL(n) GCLK_CLKCTRL_GEN_GCLK##n
72
73 /* Tick/cycle count of the last announce call. */
74 static volatile uint32_t rtc_last;
75
76 #ifndef CONFIG_TICKLESS_KERNEL
77
78 /* Current tick count. */
79 static volatile uint32_t rtc_counter;
80
81 /* Tick value of the next timeout. */
82 static volatile uint32_t rtc_timeout;
83
84 PINCTRL_DT_INST_DEFINE(0);
85 static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0);
86
87 #endif /* CONFIG_TICKLESS_KERNEL */
88
89 /*
90 * Waits for RTC bus synchronization.
91 */
rtc_sync(void)92 static inline void rtc_sync(void)
93 {
94 /* Wait for bus synchronization... */
95 #ifdef RTC_STATUS_SYNCBUSY
96 while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) {
97 }
98 #else
99 while (RTC0->SYNCBUSY.reg) {
100 }
101 #endif
102 }
103
104 /*
105 * Reads RTC COUNT register. First a read request must be written to READREQ,
106 * then - when bus synchronization completes - the COUNT register is read and
107 * returned.
108 */
rtc_count(void)109 static uint32_t rtc_count(void)
110 {
111 #ifdef RTC_READREQ_RREQ
112 RTC0->READREQ.reg = RTC_READREQ_RREQ;
113 #endif
114 rtc_sync();
115 return RTC0->COUNT.reg;
116 }
117
rtc_reset(void)118 static void rtc_reset(void)
119 {
120 rtc_sync();
121
122 /* Disable interrupt. */
123 RTC0->INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
124 /* Clear interrupt flag. */
125 RTC0->INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
126
127 /* Disable RTC module. */
128 #ifdef RTC_MODE0_CTRL_ENABLE
129 RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
130 #else
131 RTC0->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
132 #endif
133
134 rtc_sync();
135
136 /* Initiate software reset. */
137 #ifdef RTC_MODE0_CTRL_SWRST
138 RTC0->CTRL.bit.SWRST = 1;
139 while (RTC0->CTRL.bit.SWRST) {
140 }
141 #else
142 RTC0->CTRLA.bit.SWRST = 1;
143 while (RTC0->CTRLA.bit.SWRST) {
144 }
145 #endif
146 }
147
rtc_isr(const void * arg)148 static void rtc_isr(const void *arg)
149 {
150 ARG_UNUSED(arg);
151
152 /* Read and clear the interrupt flag register. */
153 uint16_t status = RTC0->INTFLAG.reg;
154
155 RTC0->INTFLAG.reg = status;
156
157 #ifdef CONFIG_TICKLESS_KERNEL
158
159 /* Read the current counter and announce the elapsed time in ticks. */
160 uint32_t count = rtc_count();
161
162 if (count != rtc_last) {
163 uint32_t ticks = (count - rtc_last) / CYCLES_PER_TICK;
164
165 sys_clock_announce(ticks);
166 rtc_last += ticks * CYCLES_PER_TICK;
167 }
168
169 #else /* !CONFIG_TICKLESS_KERNEL */
170
171 if (status) {
172 /* RTC just ticked one more tick... */
173 if (++rtc_counter == rtc_timeout) {
174 sys_clock_announce(rtc_counter - rtc_last);
175 rtc_last = rtc_counter;
176 }
177 } else {
178 /* ISR was invoked directly from sys_clock_set_timeout. */
179 sys_clock_announce(0);
180 }
181
182 #endif /* CONFIG_TICKLESS_KERNEL */
183 }
184
sys_clock_set_timeout(int32_t ticks,bool idle)185 void sys_clock_set_timeout(int32_t ticks, bool idle)
186 {
187 ARG_UNUSED(idle);
188
189 #ifdef CONFIG_TICKLESS_KERNEL
190
191 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
192 ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS);
193
194 /* Compute number of RTC cycles until the next timeout. */
195 uint32_t count = rtc_count();
196 uint32_t timeout = ticks * CYCLES_PER_TICK + count % CYCLES_PER_TICK;
197
198 /* Round to the nearest tick boundary. */
199 timeout = DIV_ROUND_UP(timeout, CYCLES_PER_TICK) * CYCLES_PER_TICK;
200
201 if (timeout < TICK_THRESHOLD) {
202 timeout += CYCLES_PER_TICK;
203 }
204
205 rtc_sync();
206 RTC0->COMP[0].reg = count + timeout;
207
208 #else /* !CONFIG_TICKLESS_KERNEL */
209
210 if (ticks == K_TICKS_FOREVER) {
211 /* Disable comparator for K_TICKS_FOREVER and other negative
212 * values.
213 */
214 rtc_timeout = rtc_counter;
215 return;
216 }
217
218 if (ticks < 1) {
219 ticks = 1;
220 }
221
222 /* Avoid race condition between reading counter and ISR incrementing
223 * it.
224 */
225 unsigned int key = irq_lock();
226
227 rtc_timeout = rtc_counter + ticks;
228 irq_unlock(key);
229
230 #endif /* CONFIG_TICKLESS_KERNEL */
231 }
232
sys_clock_elapsed(void)233 uint32_t sys_clock_elapsed(void)
234 {
235 #ifdef CONFIG_TICKLESS_KERNEL
236 return (rtc_count() - rtc_last) / CYCLES_PER_TICK;
237 #else
238 return rtc_counter - rtc_last;
239 #endif
240 }
241
sys_clock_cycle_get_32(void)242 uint32_t sys_clock_cycle_get_32(void)
243 {
244 /* Just return the absolute value of RTC cycle counter. */
245 return rtc_count();
246 }
247
sys_clock_driver_init(void)248 static int sys_clock_driver_init(void)
249 {
250 int retval;
251
252
253 #ifdef MCLK
254 MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
255 OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
256 #else
257 /* Set up bus clock and GCLK generator. */
258 PM->APBAMASK.reg |= PM_APBAMASK_RTC;
259 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN
260 | GCLK_GEN(DT_INST_PROP(0, clock_generator));
261
262 /* Synchronize GCLK. */
263 while (GCLK->STATUS.bit.SYNCBUSY) {
264 }
265 #endif
266
267 retval = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
268 if (retval < 0) {
269 return retval;
270 }
271
272 /* Reset module to hardware defaults. */
273 rtc_reset();
274
275 rtc_last = 0U;
276
277 /* Configure RTC with 32-bit mode, configured prescaler and MATCHCLR. */
278 #ifdef RTC_MODE0_CTRL_MODE
279 uint16_t ctrl = RTC_MODE0_CTRL_MODE(0) | RTC_MODE0_CTRL_PRESCALER(0);
280 #else
281 uint16_t ctrl = RTC_MODE0_CTRLA_MODE(0) | RTC_MODE0_CTRLA_PRESCALER(0);
282 #endif
283
284 #ifdef RTC_MODE0_CTRLA_COUNTSYNC
285 ctrl |= RTC_MODE0_CTRLA_COUNTSYNC;
286 #endif
287
288 #ifndef CONFIG_TICKLESS_KERNEL
289 #ifdef RTC_MODE0_CTRL_MATCHCLR
290 ctrl |= RTC_MODE0_CTRL_MATCHCLR;
291 #else
292 ctrl |= RTC_MODE0_CTRLA_MATCHCLR;
293 #endif
294 #endif
295 rtc_sync();
296 #ifdef RTC_MODE0_CTRL_MODE
297 RTC0->CTRL.reg = ctrl;
298 #else
299 RTC0->CTRLA.reg = ctrl;
300 #endif
301
302 #ifdef CONFIG_TICKLESS_KERNEL
303 /* Tickless kernel lets RTC count continually and ignores overflows. */
304 RTC0->INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
305 #else
306 /* Non-tickless mode uses comparator together with MATCHCLR. */
307 rtc_sync();
308 RTC0->COMP[0].reg = CYCLES_PER_TICK;
309 RTC0->INTENSET.reg = RTC_MODE0_INTENSET_OVF;
310 rtc_counter = 0U;
311 rtc_timeout = 0U;
312 #endif
313
314 /* Enable RTC module. */
315 rtc_sync();
316 #ifdef RTC_MODE0_CTRL_ENABLE
317 RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
318 #else
319 RTC0->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
320 #endif
321
322 /* Enable RTC interrupt. */
323 NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
324 IRQ_CONNECT(DT_INST_IRQN(0),
325 DT_INST_IRQ(0, priority), rtc_isr, 0, 0);
326 irq_enable(DT_INST_IRQN(0));
327
328 return 0;
329 }
330
331 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
332 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
333
