1 /*******************************************************************************
2 * @file rsi_rom_ulpss_clk.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 // Includes
31
32 #ifndef __RSI_ROM_ULPSS_CLK_H__
33 #define __RSI_ROM_ULPSS_CLK_H__
34
35 #include "rsi_rom_egpio.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * \ingroup RSI_SPECIFIC_DRIVERS
43 */
44
45 /**
46 * \defgroup RSI_CHIP_CLOCK_DRIVERS CLOCK
47 * @{
48 *
49 */
50
51 /**
52 * \defgroup RSI_ULPSS_CLOCK_DRIVERS ULPSS CLOCK
53 * @{
54 *
55 */
56 #include "rsi_ccp_user_config.h"
57 #include "rsi_packing.h"
58 #include "rsi_ulpss_clk.h"
59 #if defined(A11_ROM)
60 #include "rsi_rom_table_si91x.h"
61 #else
62 #include "rsi_rom_table_RS1xxxx.h"
63 #endif
64 #if SL_WIFI_COMPONENT_INCLUDED
65 #include "sl_rsi_utility.h"
66 #include "rsi_m4.h"
67 #endif
68
69 /**
70 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource)
71 * @brief This API is used to select the ULPSS processor ref clk configuration
72 * @param[in] clkSource : Enum values of clock source to select as ulp processor ref clock.Please refer #ULPSS_REF_CLK_SEL_T
73 * @return returns 0 \ref RSI_OK on success ,Error code on failure
74 */
RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource)75 STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource)
76 {
77 #if SL_WIFI_COMPONENT_INCLUDED
78 if (clkSource == ULPSS_40MHZ_CLK) {
79 /* Notify NWP that M4 requires XTAL clock source */
80 sli_si91x_xtal_turn_on_request_from_m4_to_TA();
81 }
82 #endif
83 return ulpss_ref_clk_config(clkSource);
84 }
85
86 /**
87 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor)
88 * @brief This API is used to select the ULPSS processor clock source when input is soc clk source which is greater than 100MHz
89 * @param[in] pCLK : Pointer to the pll register instance
90 * @param[in] clkEnable : is to enable or disable the ulpss_soc clock
91 * - Enable 1: Enables the clock
92 * - Disable 0: Disables the clock
93 * @param[in] divFactor : To divide the clock, ensure that oddDivFactor is 0 then divFactor must be even value or else odd value
94 * @param[in] oddDivFactor : Selects the type of divider for m4_soc_clk_2ulpss
95 * - 0 => Clock Divider(even) is selected
96 * - 1 => Odd Divider is selected
97 * @return returns 0 \ref RSI_OK on success ,Error code on failure
98 */
RSI_ULPSS_ClockConfig(M4CLK_Type * pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor)99 STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,
100 boolean_t clkEnable,
101 uint16_t divFactor,
102 boolean_t oddDivFactor)
103 {
104 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
105 return ROMAPI_ULPSS_CLK_API->ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor);
106 #else
107 return ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor);
108 #endif
109 }
110
111 /**
112 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK ,
113 ULP_PROC_CLK_SELECT_T clkSource,
114 uint16_t divFactor,cdDelay delayFn)
115 * @brief This API is used to configure the ULPSS processor clock source
116 * @param[in] pULPCLK : Pointer to the ulp clock register instance
117 * @param[in] clkSource : Enum values of clock source to select as processor clock.Please refer #ULP_PROC_CLK_SELECT_T and refer NOTE
118 * @param[in] divFactor : To divide the clock
119 * @param[in] delayFn : delay enable parameter is 1 for enable 0 for not enable.
120 * @return returns 0 \ref RSI_OK on success ,Error code on failure
121 * @note
122 * In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins
123 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
124 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
125 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
126 */
RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type * pULPCLK,ULP_PROC_CLK_SELECT_T clkSource,uint16_t divFactor,cdDelay delayFn)127 STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK,
128 ULP_PROC_CLK_SELECT_T clkSource,
129 uint16_t divFactor,
130 cdDelay delayFn)
131 {
132 return ulpss_ulp_proc_clk_config(pULPCLK, clkSource, divFactor, delayFn);
133 }
134
135 /**
136 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags)
137 * @brief This API is used to enable different pheriheral clocks in ULPSS
138 * @param[in] pULPCLK : Pointer to the ulp clock register instance
139 * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral
140 * - \ref Possible values for this parameter are
141 * - \ref ULPSS_TASS_QUASI_SYNC
142 * - \ref ULPSS_M4SS_SLV_SEL
143 * - \ref AUX_SOC_EXT_TRIG_2_SEL
144 * - \ref AUX_SOC_EXT_TRIG_1_SEL
145 * - \ref AUX_ULP_EXT_TRIG_2_SEL
146 * - \ref AUX_ULP_EXT_TRIG_1_SEL
147 * - \ref TIMER_PCLK_EN
148 * - \ref EGPIO_PCLK_ENABLE
149 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
150 * - \ref CLK_ENABLE_ULP_MEMORIES
151 * - \ref VAD_CLK_EN
152 * - \ref FIM_CLK_EN
153 * - \ref REG_ACCESS_SPI_CLK_EN
154 * - \ref EGPIO_CLK_EN
155 * - \ref CLK_ENABLE_TIMER
156 * - \ref VAD_PCLK_ENABLE
157 * - \ref FIM_PCLK_ENABLE
158 * - \ref SCLK_ENABLE_UART
159 * - \ref PCLK_ENABLE_UART
160 * - \ref SCLK_ENABLE_SSI_MASTER
161 * - \ref PCLK_ENABLE_SSI_MASTER
162 * - \ref CLK_ENABLE_I2S
163 * - \ref PCLK_ENABLE_I2C
164 * - \ref RELEASE_SOFT_RESET
165 * - \ref PCM_FSYNC_START
166 * - \ref PCM_ENABLE
167 * @return returns 0 \ref RSI_OK on success ,Error code on failure
168 */
RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type * pULPCLK,uint32_t u32Flags)169 STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags)
170 {
171 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
172 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags);
173 #else
174 return ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags);
175 #endif
176 }
177
178 /**
179 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags)
180 * @brief This API is used to disable different peripheral clocks in ULPSS
181 * @param[in] pULPCLK : Pointer to the ulp clock register instance
182 * @param[in] u32Flags is to Ored value of the clock enable bits of particular peripheral
183 * \n Possible values for this parameter are
184 * - \ref ULPSS_TASS_QUASI_SYNC
185 * - \ref ULPSS_M4SS_SLV_SEL
186 * - \ref AUX_SOC_EXT_TRIG_2_SEL
187 * - \ref AUX_SOC_EXT_TRIG_1_SEL
188 * - \ref AUX_ULP_EXT_TRIG_2_SEL
189 * - \ref AUX_ULP_EXT_TRIG_1_SEL
190 * - \ref TIMER_PCLK_EN
191 * - \ref EGPIO_PCLK_ENABLE
192 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
193 * - \ref CLK_ENABLE_ULP_MEMORIES
194 * - \ref VAD_CLK_EN
195 * - \ref FIM_CLK_EN
196 * - \ref REG_ACCESS_SPI_CLK_EN
197 * - \ref EGPIO_CLK_EN
198 * - \ref CLK_ENABLE_TIMER
199 * - \ref VAD_PCLK_ENABLE
200 * - \ref FIM_PCLK_ENABLE
201 * - \ref SCLK_ENABLE_UART
202 * - \ref PCLK_ENABLE_UART
203 * - \ref SCLK_ENABLE_SSI_MASTER
204 * - \ref PCLK_ENABLE_SSI_MASTER
205 * - \ref CLK_ENABLE_I2S
206 * - \ref PCLK_ENABLE_I2C
207 * - \ref RELEASE_SOFT_RESET
208 * - \ref PCM_FSYNC_START
209 * - \ref PCM_ENABLE
210 * @return returns 0 \ref RSI_OK on success ,Error code on failure
211 */
RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type * pULPCLK,uint32_t u32Flags)212 STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags)
213 {
214 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
215 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags);
216 #else
217 return ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags);
218 #endif
219 }
220 /**
221 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags)
222 * @brief This API is used to enable different peripheral clocks in ULPSS
223 * @param[in] pULPCLK : Pointer to the ulp clock register instance
224 * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral
225 * \n Possible values for this parameter are
226 * - \ref ULPSS_TASS_QUASI_SYNC
227 * - \ref ULPSS_M4SS_SLV_SEL
228 * - \ref AUX_SOC_EXT_TRIG_2_SEL
229 * - \ref AUX_SOC_EXT_TRIG_1_SEL
230 * - \ref AUX_ULP_EXT_TRIG_2_SEL
231 * - \ref AUX_ULP_EXT_TRIG_1_SEL
232 * - \ref TIMER_PCLK_EN
233 * - \ref EGPIO_PCLK_ENABLE
234 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
235 * - \ref CLK_ENABLE_ULP_MEMORIES
236 * - \ref VAD_CLK_EN
237 * - \ref FIM_CLK_EN
238 * - \ref REG_ACCESS_SPI_CLK_EN
239 * - \ref EGPIO_CLK_EN
240 * - \ref CLK_ENABLE_TIMER
241 * - \ref VAD_PCLK_ENABLE
242 * - \ref FIM_PCLK_ENABLE
243 * - \ref SCLK_ENABLE_UART
244 * - \ref PCLK_ENABLE_UART
245 * - \ref SCLK_ENABLE_SSI_MASTER
246 * - \ref PCLK_ENABLE_SSI_MASTER
247 * - \ref CLK_ENABLE_I2S
248 * - \ref PCLK_ENABLE_I2C
249 * - \ref RELEASE_SOFT_RESET
250 * - \ref PCM_FSYNC_START
251 * - \ref PCM_ENABLE
252 * @return returns 0 \ref RSI_OK on success ,Error code on failure
253 */
RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type * pULPCLK,uint32_t u32Flags)254 STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags)
255 {
256 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
257 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags);
258 #else
259 return ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags);
260 #endif
261 }
262 /**
263 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags)
264 * @brief This API is used to disable different peripheral clocks in ULPSS
265 * @param[in] pULPCLK : Pointer to the ulp clock register instance
266 * @param[in] u32Flags : is to Ored value of the clock enable bits of particular peripheral
267 * \n Possible values for this parameter are
268 * - \ref ULPSS_TASS_QUASI_SYNC
269 * - \ref ULPSS_M4SS_SLV_SEL
270 * - \ref AUX_SOC_EXT_TRIG_2_SEL
271 * - \ref AUX_SOC_EXT_TRIG_1_SEL
272 * - \ref AUX_ULP_EXT_TRIG_2_SEL
273 * - \ref AUX_ULP_EXT_TRIG_1_SEL
274 * - \ref TIMER_PCLK_EN
275 * - \ref EGPIO_PCLK_ENABLE
276 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
277 * - \ref CLK_ENABLE_ULP_MEMORIES
278 * - \ref VAD_CLK_EN
279 * - \ref FIM_CLK_EN
280 * - \ref REG_ACCESS_SPI_CLK_EN
281 * - \ref EGPIO_CLK_EN
282 * - \ref CLK_ENABLE_TIMER
283 * - \ref VAD_PCLK_ENABLE
284 * - \ref FIM_PCLK_ENABLE
285 * - \ref SCLK_ENABLE_UART
286 * - \ref PCLK_ENABLE_UART
287 * - \ref SCLK_ENABLE_SSI_MASTER
288 * - \ref PCLK_ENABLE_SSI_MASTER
289 * - \ref CLK_ENABLE_I2S
290 * - \ref PCLK_ENABLE_I2C
291 * - \ref RELEASE_SOFT_RESET
292 * - \ref PCM_FSYNC_START
293 * - \ref PCM_ENABLE
294 * @return returns 0 \ref RSI_OK on success ,Error code on failure
295 */
RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type * pULPCLK,uint32_t u32Flags)296 STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags)
297 {
298 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
299 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags);
300 #else
301 return ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags);
302 #endif
303 }
304
305 /**
306 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType ,
307 ULP_SSI_CLK_SELECT_T clkSource,
308 uint16_t divFactor)
309 * @brief This API is used to configure the SSI clock source
310 * @param[in] pULPCLK : Pointer to the ulp clock register instance
311 * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info
312 * @param[in] clkSource : Value of clock source to select as Ulp SSI clock. Please refer #ULP_SSI_CLK_SELECT_T for more info
313 * - 0: \ref_clk (output of dynamic clock mux for different possible ref_clk sources)
314 * - 1: \ref ulp_32khz_ro_clk
315 * - 2: \ref ulp_32khz_rc_clk
316 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
317 * - 4: \ref ulp_mhz_rc_clk
318 * - 5: \ref ulp_20mhz_ro_clk
319 * - 6: \ref soc_clk #refer NOTE
320 * @param[in] divFactor : To divide the clock
321 * @return returns 0 \ref RSI_OK on success ,Error code on failure
322 * @note There are two \ref XTAL Clk sources one is Internal and external \ref XTAL clk source. In order to enable the external XTAL clk source need to configure the \ref NPSS_GPIO pins
323 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
324 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
325 * - please refer \ref RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
326 */
327
RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type * pULPCLK,CLK_ENABLE_T clkType,ULP_SSI_CLK_SELECT_T clkSource,uint16_t divFactor)328 STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK,
329 CLK_ENABLE_T clkType,
330 ULP_SSI_CLK_SELECT_T clkSource,
331 uint16_t divFactor)
332 {
333 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
334 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor);
335 #else
336 return ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor);
337 #endif
338 }
339
340 /**
341 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK,
342 ULP_I2S_CLK_SELECT_T clkSource ,
343 uint16_t divFactor)
344 * @brief This API is used to configure the I2S clock source
345 * @param[in] pULPCLK : Pointer to the ulp clock register instance
346 * @param[in] clkSource : Value of clock source to select as I2S clock. Please refer #ULP_SSI_CLK_SELECT_T for more info
347 * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
348 * - 1: \ref ulp_32khz_ro_clk
349 * - 2: \ref ulp_32khz_rc_clk
350 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
351 * - 4: \ref ulp_mhz_rc_clk
352 * - 5: \ref ulp_20mhz_ro_clk
353 * - 6: \ref soc_clk #refer NOTE
354 * - 7: \ref ulp_doubler_clk
355 * - 8: \ref I2S PLL
356 * @param[in] divFactor : To divide the clock
357 * @return returns 0 \ref RSI_OK on success ,Error code on failure
358 * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
359 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
360 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
361 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
362 */
RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type * pULPCLK,ULP_I2S_CLK_SELECT_T clkSource,uint16_t divFactor)363 STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK,
364 ULP_I2S_CLK_SELECT_T clkSource,
365 uint16_t divFactor)
366 {
367 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
368 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor);
369 #else
370 return ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor);
371 #endif
372 }
373
374 /**
375 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK,CLK_ENABLE_T clkType,
376 boolean_t bFrClkSel,ULP_UART_CLK_SELECT_T clkSource ,
377 uint16_t divFactor)
378 * @brief This API is used to configure the UART clock source
379 * @param[in] pULPCLK : Pointer to the ulp clock register instance
380 * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info
381 * @param[in] bFrClkSel : To enable or disable ulp uart clk selection
382 * - 1: Fractional Divider output is selected
383 * - 0: Swallow Divider output is selected
384 * @param[in] clkSource : Value of clock source to select as processor clock
385 * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
386 * - 1: \ref ulp_32khz_ro_clk
387 * - 2: \ref ulp_32khz_rc_clk
388 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
389 * - 4: \ref ulp_mhz_rc_clk
390 * - 5: \ref ulp_20mhz_ro_clk
391 * - 6: \ref soc_clk #refer NOTE
392 * @param[in] divFactor : To divide the clock
393 * @return returns 0 \ref RSI_OK on success ,Error code on failure
394 * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
395 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
396 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
397 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
398 */
RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type * pULPCLK,CLK_ENABLE_T clkType,boolean_t bFrClkSel,ULP_UART_CLK_SELECT_T clkSource,uint16_t divFactor)399 STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK,
400 CLK_ENABLE_T clkType,
401 boolean_t bFrClkSel,
402 ULP_UART_CLK_SELECT_T clkSource,
403 uint16_t divFactor)
404 {
405 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
406 return ROMAPI_ULPSS_CLK_API->ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor);
407 #else
408 return ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor);
409 #endif
410 }
411 /**
412 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType,
413 boolean_t bTmrSync ,ULP_TIMER_CLK_SELECT_T clkSource,
414 uint8_t skipSwitchTime)
415 * @brief This API is used to configure the timer clock source
416 * @param[in] pULPCLK : Pointer to the ulp clock register instance
417 * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info
418 * @param[in] bTmrSync : To enable Ulp timer in synchronous mode to ULPSS pclk
419 * - 1: Enables
420 * - 0: Disables
421 * @param[in] clkSource : Value of clock source to select as Timer clock. Please refer #ULP_TIMER_CLK_SELECT_T for possible values
422 * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
423 * - 1: \ref ulp_32khz_ro_clk
424 * - 2: \ref ulp_32khz_rc_clk
425 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
426 * - 4: \ref ulp_mhz_rc_clk
427 * - 5: \ref ulp_20mhz_ro_clk
428 * - 6: \ref soc_clk #refer NOTE
429 * - 7: \ref ulp_doubler_clk
430 * @param[in] skipSwitchTime : To skip the switching of timer clk.
431 * - 1 : Wait for switching timer clk
432 * - 0 : Skip waiting for switching timer clk
433 * @return returns 0 \ref RSI_OK on success ,Error code on failure
434 * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
435 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
436 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
437 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
438 */
RSI_ULPSS_TimerClkConfig(ULPCLK_Type * pULPCLK,CLK_ENABLE_T clkType,boolean_t bTmrSync,ULP_TIMER_CLK_SELECT_T clkSource,uint8_t skipSwitchTime)439 STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK,
440 CLK_ENABLE_T clkType,
441 boolean_t bTmrSync,
442 ULP_TIMER_CLK_SELECT_T clkSource,
443 uint8_t skipSwitchTime)
444 {
445 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
446 return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime);
447 #else
448 return ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime);
449 #endif
450 }
451
452 /**
453 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK )
454 * @brief This API is used to disable the timer clock source
455 * @param[in] pULPCLK : Pointer to the ulp clock register instance
456 * @return returns 0 \ref RSI_OK on success ,Error code on failure
457 */
RSI_ULPSS_TimerClkDisable(ULPCLK_Type * pULPCLK)458 STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK)
459 {
460 #if defined(CHIP_9118) && defined(A11_ROM) && defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
461 return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_disable(pULPCLK);
462 #else
463 return ulpss_time_clk_disable(pULPCLK);
464 #endif
465 }
466
467 /**
468 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK ,
469 CLK_ENABLE_T clkType,
470 ULP_AUX_CLK_SELECT_T clkSource
471 )
472 * @brief This API is used to configure the AUX clock source
473 * @param[in] pULPCLK : Pointer to the ulp clock register instance
474 * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info
475 * @param[in] clkSource : Value of clock source to select as AUX clock. Please refer #ULP_AUX_CLK_SELECT_T for more info
476 * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
477 * - 1: \ref ulp_32khz_ro_clk
478 * - 2: \ref ulp_32khz_rc_clk
479 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
480 * - 4: \ref ulp_mhz_rc_clk
481 * - 5: \ref ulp_20mhz_ro_clk
482 * - 6: \ref soc_clk #refer NOTE
483 * - 7: \ref ulp_doubler_clk
484 * - 8: \ref I2S PLL
485 * @return returns 0 \ref RSI_OK on success ,Error code on failure
486 * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
487 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
488 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
489 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
490 */
RSI_ULPSS_AuxClkConfig(ULPCLK_Type * pULPCLK,CLK_ENABLE_T clkType,ULP_AUX_CLK_SELECT_T clkSource)491 STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK,
492 CLK_ENABLE_T clkType,
493 ULP_AUX_CLK_SELECT_T clkSource)
494 {
495 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
496 return ROMAPI_ULPSS_CLK_API->ulpss_aux_clk_config(pULPCLK, clkType, clkSource);
497 #else
498 return ulpss_aux_clk_config(pULPCLK, clkType, clkSource);
499 #endif
500 }
501
502 /**
503 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK ,
504 ULP_VAD_CLK_SELECT_T clkSource ,
505 ULP_VAD_FCLK_SELECT_T FclkSource ,
506 uint16_t divFactor)
507 * @brief This API is used to configure the VAD clock source
508 * @param[in] pULPCLK : Pointer to the ulp clock register instance
509 * @param[in] clkSource : Value of clock source to select as vad clock. Please refer #ULP_VAD_CLK_SELECT_T for more info
510 * - 0: \ref ulp_32khz_ro_clk
511 * - 1: \ref ulp_32khz_rc_clk
512 * - 2: \ref ulp_32khz_xtal_clk #refer NOTE
513 * \n NOTE: In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins
514 * \n which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
515 * @param[in] FclkSource : Ulp vad Fast clock select. Please refer #ULP_VAD_FCLK_SELECT_T for more info
516 * - 0: ulpss processor clock #refer NOTE
517 * - 1: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
518 * - 2: \ref ulp_mhz_rc_clk
519 * - 3: \ref ulp_20mhz_ro_clk
520 * - 4: \ref soc_clk #refer NOTE
521 * @param[in] divFactor : To divide the clock
522 * @return returns 0 \ref RSI_OK on success ,Error code on failure
523 * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
524 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
525 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
526 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
527 * - In order to enable the ulpss processor clock source need to configure the
528 * - RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK ,boolean_t clkEnable,uint8_t clkSource,uint16_t divFactor,delayMs cbDelay )
529 */
RSI_ULPSS_VadClkConfig(ULPCLK_Type * pULPCLK,ULP_VAD_CLK_SELECT_T clkSource,ULP_VAD_FCLK_SELECT_T FclkSource,uint16_t divFactor)530 STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK,
531 ULP_VAD_CLK_SELECT_T clkSource,
532 ULP_VAD_FCLK_SELECT_T FclkSource,
533 uint16_t divFactor)
534 {
535 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
536 return ROMAPI_ULPSS_CLK_API->ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor);
537 #else
538 return ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor);
539 #endif
540 }
541 /**
542 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK ,ULP_TOUCH_CLK_SELECT_T clkSource ,
543 uint16_t divFactor )
544 * @brief This API is used to configure the Touch clock source
545 * @param[in] pULPCLK : Pointer to the ulp clock register instance
546 * @param[in] clkSource : Value of clock source to select as Touch clock. Please refer #ULP_TOUCH_CLK_SELECT_T for more info.
547 * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources)
548 * - 1: \ref ulp_32khz_ro_clk
549 * - 2: \ref ulp_32khz_rc_clk
550 * - 3: \ref ulp_32khz_xtal_clk #refer NOTE
551 * - 4: \ref ulp_mhz_rc_clk
552 * - 5: \ref ulp_20mhz_ro_clk
553 * - 6: \ref soc_clk #refer NOTE
554 * @param[in] divFactor : To divide the clock
555 * @return returns 0 \ref RSI_OK on success ,Error code on failure
556 * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins
557 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
558 * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk
559 * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor);
560 */
RSI_ULPSS_TouchClkConfig(ULPCLK_Type * pULPCLK,ULP_TOUCH_CLK_SELECT_T clkSource,uint16_t divFactor)561 STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK,
562 ULP_TOUCH_CLK_SELECT_T clkSource,
563 uint16_t divFactor)
564 {
565 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
566 return ROMAPI_ULPSS_CLK_API->ulpss_touch_clk_config(pULPCLK, clkSource, divFactor);
567 #else
568 return ulpss_touch_clk_config(pULPCLK, clkSource, divFactor);
569 #endif
570 }
571 /**
572 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK , boolean_t clkEnable ,uint32_t divFactor)
573 * @brief This API is used to configure the sleep sensor clock source
574 * @param[in] pULPCLK : Pointer to the ulp clock register instance
575 * @param[in] clkEnable : To enable or disable the sleep sensor clock
576 * - Enable 1: Enables the clock
577 * - Disable 0: Disables the clock
578 * @param[in] divFactor : To divide the clock
579 * @return returns 0 \ref RSI_OK on success ,Error code on failure
580 * @note In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins
581 * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first
582 */
RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type * pULPCLK,boolean_t clkEnable,uint32_t divFactor)583 STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor)
584 {
585 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
586 return ROMAPI_ULPSS_CLK_API->ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor);
587 #else
588 return ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor);
589 #endif
590 }
591
592 /**
593 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK,
594 ULPPERIPHERALS_CLK_T module,CLK_ENABLE_T clkType)
595 * @brief This API is used to enable the particular ULP peripherial Clock
596 * @param[in] pULPCLK : Pointer to the ulp clock register instance
597 * @param[in] module : To select particular ulp pheripheral. See \ref ULPPERIPHERALS_ENABLE_T for more info.
598 * @param[in] clkType :To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info
599 * @return returns 0 \ref RSI_OK on success ,Error code on failure
600 */
RSI_ULPSS_PeripheralEnable(ULPCLK_Type * pULPCLK,ULPPERIPHERALS_CLK_T module,CLK_ENABLE_T clkType)601 STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK,
602 ULPPERIPHERALS_CLK_T module,
603 CLK_ENABLE_T clkType)
604 {
605 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
606 return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_enable(pULPCLK, module, clkType);
607 #else
608 return ulpss_peripheral_enable(pULPCLK, module, clkType);
609 #endif
610 }
611 /**
612 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module)
613 * @brief This API is used to Disable the particular ULP peripherial Clock
614 * @param[in] pULPCLK : Pointer to the ulp clock register instance
615 * @param[in] module : To select particular ulp pheripheral. \ref ULPPERIPHERALS_DISABLE_T for more info.
616 * @return returns 0 \ref RSI_OK on success ,Error code on failure
617 */
RSI_ULPSS_PeripheralDisable(ULPCLK_Type * pULPCLK,ULPPERIPHERALS_CLK_T module)618 STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module)
619 {
620 #if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT)
621 return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_disable(pULPCLK, module);
622 #else
623 return ulpss_peripheral_disable(pULPCLK, module);
624 #endif
625 }
626
627 rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource);
628
629 rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor);
630
631 rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK,
632 ULP_PROC_CLK_SELECT_T clkSource,
633 uint16_t divFactor,
634 cdDelay delayFn);
635
636 rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags);
637
638 rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags);
639
640 rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags);
641
642 rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags);
643
644 rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK,
645 CLK_ENABLE_T clkType,
646 ULP_SSI_CLK_SELECT_T clkSource,
647 uint16_t divFactor);
648
649 rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor);
650
651 rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK,
652 CLK_ENABLE_T clkType,
653 boolean_t bFrClkSel,
654 ULP_UART_CLK_SELECT_T clkSource,
655 uint16_t divFactor);
656
657 rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK,
658 CLK_ENABLE_T clkType,
659 boolean_t bTmrSync,
660 ULP_TIMER_CLK_SELECT_T clkSource,
661 uint8_t skipSwitchTime);
662
663 rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource);
664
665 rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK,
666 ULP_VAD_CLK_SELECT_T clkSource,
667 ULP_VAD_FCLK_SELECT_T FclkSource,
668 uint16_t divFactor);
669
670 rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor);
671
672 rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor);
673
674 rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType);
675
676 rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module);
677
678 #ifdef __cplusplus
679 }
680 #endif
681
682 #endif /*__RSI_ROM_ULPSS_CLK_H__*/
683
684 /*@} end of RSI_ULPSS_CLOCK_DRIVERS */
685
686 /* @} end ofRSI_CHIP_CLOCK_DRIVERS */
687
