1 /***************************************************************************/ /** 2 * @file rsi_m4.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 #ifndef _RSI_M4_HAL_H_ 31 #define _RSI_M4_HAL_H_ 32 #ifdef SLI_SI91X_MCU_INTERFACE 33 34 #include "rsi_pkt_mgmt.h" 35 #include "sl_device.h" 36 #include "sl_status.h" 37 38 /****************************************************** 39 * * Constants 40 * ******************************************************/ 41 42 #define M4_ISR_IRQ 74 43 44 #define TA_MEMORY_OFFSET_ADDRESS 0x00400000 45 #if defined(SLI_SI917) || defined(SLI_SI915) 46 #define M4_MEMORY_OFFSET_ADDRESS 0x00500000 47 #else 48 #define M4_MEMORY_OFFSET_ADDRESS 0x00200000 49 #endif 50 51 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 52 53 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 54 #ifndef NVIC 55 #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ 56 #endif 57 58 #define M4SS_P2P_INT_BASE_ADDRESS 0x46008000 59 #define MCU_PWR_CTRL_BASE_ADDR 0x24048400 60 #define MISC_CFG_HOST_CTRL *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x0C) 61 #ifndef M4SS_P2P_INTR_SET_REG 62 #define M4SS_P2P_INTR_SET_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x16C) 63 #endif 64 #ifndef M4SS_P2P_INTR_CLR_REG 65 #define M4SS_P2P_INTR_CLR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x170) 66 #endif 67 #define P2P_STATUS_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x174) 68 #define TASS_P2P_INTR_MASK_SET *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x178) 69 #define TASS_P2P_INTR_MASK_CLR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x17C) 70 #define TASS_P2P_INTR_CLEAR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x180) 71 72 #define TASS_P2P_INT_BASE_ADDRESS 0x41050000 73 74 #define TASS_P2P_INTR_SET_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x8C) 75 #define TASS_P2P_INTR_CLR_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x90) 76 77 #define M4_TX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x34) 78 #define M4_RX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x5C) 79 #define HOST_INTR_STATUS_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x04) 80 81 #define DMA_DESC_REG_VALID (0xA0 << 8) 82 83 #define TA_wakeup_M4 BIT(2) 84 #define TA_is_active BIT(3) 85 #define M4_wakeup_TA BIT(0) 86 #define M4_is_active BIT(1) 87 88 /*Macro used to define the PTE CRC value of the Firmware 17 Boards*/ 89 #define FIRMWARE_17_PTE_CRC_VALUE 0 90 91 /*Macro used to notify NWP about M4 XTAL usage*/ 92 #define TURN_ON_XTAL_REQUEST BIT(9) 93 #define TURN_OFF_XTAL_REQUEST BIT(10) 94 #define M4_IS_USING_XTAL_REQUEST BIT(11) 95 96 #define ARM_MASK_1 0xE000E100 97 #define ARM_MASK_1 0xE000E100 98 #define ARM_MASK_1 0xE000E100 99 100 #ifndef BIT 101 #define BIT(x) (1 << (x)) 102 #endif 103 104 //! This interrupt is raised by M4 to NWP when there is a TX packet from M4 to read 105 #define RX_BUFFER_VALID BIT(1) 106 #define TX_PKT_PENDING_INTERRUPT BIT(2) 107 #define UPGRADE_M4_IMAGE BIT(5) 108 #if defined(SLI_SI917) || defined(SLI_SI915) 109 #define M4_WAITING_FOR_TA_TO_WR_ON_FLASH BIT(6) 110 #endif 111 #ifdef SL_SI91X_SIDE_BAND_CRYPTO 112 #define SIDE_BAND_CRYPTO_INTR BIT(7) 113 #endif 114 #define M4_WAITING_FOR_TA_DEINIT BIT(8) 115 116 #define TX_PKT_TRANSFER_DONE_INTERRUPT BIT(2) 117 //! This interrupt is received from NWP when RX packet is pending from NWP 118 #define RX_PKT_TRANSFER_DONE_INTERRUPT BIT(1) 119 //! This interrupt is received from NWP when TX packet transfer from M4 to NWP is done 120 121 #define M4_IMAGE_UPGRADATION_PENDING_INTERRUPT BIT(4) 122 //! This interrupt is raised by NWP to M4 when there is a TX packet from M4 to read 123 124 #if defined(SLI_SI917) || defined(SLI_SI915) 125 //! This interrupt is raised by NWP to M4 when there is a flash write request from M4 to NWP in common flash mode 126 #define TA_WRITING_ON_COMM_FLASH BIT(5) 127 #endif 128 129 #ifdef SL_SI91X_SIDE_BAND_CRYPTO 130 #define SIDE_BAND_CRYPTO_DONE BIT(6) 131 #endif 132 #define NWP_DEINIT_IN_COMM_FLASH BIT(7) 133 134 //! This interrupt is received from TA when RSI_BUFFER_FULL is clear in TA 135 #define TA_RSI_BUFFER_FULL_CLEAR_EVENT BIT(8) 136 137 #if defined(SLI_SI917) || defined(SLI_SI915) 138 //! Option value for m4 app from flash to ram API 139 #define UPGRADE_M4_IMAGE_OTA 1 140 #define TA_WRITES_ON_COMM_FLASH 2 141 #define M4_WAIT_FOR_NWP_DEINIT 3 142 #endif 143 144 #ifdef SLI_SI91X_ENABLE_OS 145 #define TASS_P2P_INTR_PRI 5 146 #define SYSTICK_INTR_PRI 7 147 #else 148 #define TASS_P2P_INTR_PRI 5 149 #define SYSTICK_INTR_PRI (1 << __NVIC_PRIO_BITS) - 1 150 #endif 151 /****************************************************** 152 * * Enumerations 153 * ******************************************************/ 154 155 /****************************************************** 156 * * Type Definitions 157 * ******************************************************/ 158 typedef struct rsi_m4ta_desc_dword1_s { 159 //! Reserved 160 uint32_t reserved : 15; 161 162 //! 1 bit : indicates the presence of more descriptors 163 //! 1 - last descriptor 164 //! 0 - more descriptors are present 165 uint32_t last_desc : 1; 166 167 //! Buffer queue_no to be transfered for this descriptor 168 uint32_t queue_no : 4; 169 170 //! Buffer length to be transfered for this descriptor 171 uint32_t length : 12; 172 173 } rsi_m4ta_desc_dword1_t; 174 175 typedef struct rsi_m4ta_desc_s { 176 //! source address 177 uint32_t addr; 178 179 uint16_t length; 180 //! descriptor control fields 181 182 } rsi_m4ta_desc_t; 183 184 //! host descriptor structure 185 typedef struct rsi_frame_desc_s { 186 //! Data frame body length. Bits 14:12=queue, 000 for data, Bits 11:0 are the length 187 uint8_t frame_len_queue_no[2]; 188 //! Frame type 189 uint8_t frame_type; 190 //! Unused , set to 0x00 191 uint8_t reserved[9]; 192 //! Management frame descriptor response status, 0x00=success, else error 193 uint8_t status; 194 uint8_t reserved1[3]; 195 } rsi_frame_desc_t; 196 197 //! P2P registers Backup structure 198 typedef struct rsi_p2p_intr_status_bkp_s { 199 uint32_t tass_p2p_intr_mask_clr_bkp; 200 uint32_t m4ss_p2p_intr_set_reg_bkp; 201 } rsi_p2p_intr_status_bkp_t; 202 203 /****************************************************** 204 * * Structures 205 * ******************************************************/ 206 207 /****************************************************** 208 * * Global Variables 209 * ******************************************************/ 210 /****************************************************** 211 * * Function Declarations 212 * ******************************************************/ 213 int16_t rsi_frame_write(rsi_frame_desc_t *uFrameDscFrame, uint8_t *payloadparam, uint16_t size_param); 214 rsi_pkt_t *rsi_frame_read(void); 215 int16_t rsi_device_interrupt_status(uint8_t *int_status); 216 217 sl_status_t sli_m4_interrupt_isr(void); 218 void sli_m4_ta_interrupt_init(void); 219 void sli_si91x_raise_pkt_pending_interrupt_to_ta(void); 220 #ifdef SL_SI91X_SIDE_BAND_CRYPTO 221 void sli_si91x_raise_side_band_interrupt_to_ta(void); 222 #endif 223 int32_t rsi_send_pkt_to_ta(rsi_m4ta_desc_t *tx_desc); 224 void rsi_transfer_to_ta_done_isr(void); 225 void rsi_pkt_pending_from_ta_isr(void); 226 sl_status_t sli_receive_from_ta_done_isr(void); 227 int16_t rsi_device_buffer_full_status(void); 228 int rsi_submit_rx_pkt(void); 229 void unmask_ta_interrupt(uint32_t interrupt_no); 230 void mask_ta_interrupt(uint32_t interrupt_no); 231 void raise_m4_to_ta_interrupt(uint32_t interrupt_no); 232 void clear_m4_to_ta_interrupt(uint32_t interrupt_no); 233 void clear_ta_interrupt_mask(void); 234 void set_ta_interrupt_mask(void); 235 void clear_ta_to_m4_interrupt(uint32_t interrupt_no); 236 void sl_mv_m4_app_from_flash_to_ram(int option); 237 uint32_t NVIC_GetIRQEnable(IRQn_Type IRQn); 238 void sli_si91x_config_m4_dma_desc_on_reset(void); 239 void rsi_update_tx_dma_desc(uint8_t skip_dma_valid); 240 void rsi_update_rx_dma_desc(void); 241 sl_status_t si91x_req_wakeup(void); 242 void sl_si91x_ta_events_init(void); /*Function used to create and initialize event mechanism for NWP related events */ 243 bool sli_si91x_is_m4_using_xtal(void); 244 bool sli_si91x_is_xtal_in_use_by_m4(void); 245 void sli_si91x_set_m4_is_using_xtal(void); 246 void sli_si91x_set_xtal_in_use_by_m4(void); 247 void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void); 248 void sli_si91x_xtal_turn_off_request_from_m4_to_TA(void); 249 void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t xtal_enable); 250 void sli_si91x_send_m4_xtal_usage_notification_to_ta(void); 251 void sli_si91x_clear_xtal_in_use_by_m4(void); 252 #endif 253 #endif 254
