1 /***************************************************************************/ /**
2 * @file rsi_gpdma.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 // Includes Files
31
32 #include "rsi_ccp_common.h"
33 #include "base_types.h"
34 #include "rsi_error.h"
35 #include "rsi_packing.h"
36
37 #ifndef RSI_GPDMA_H
38 #define RSI_GPDMA_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #define RSI_GPDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // API version
45 #define RSI_GPDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version
46
47 #define GPDMA_CHANNEL_NUM 7
48
49 // GPDMA Status Flags
50 #define GPDMA_STAT_HRESP_ERROR0 (1UL << 0) // Channel0 dma error
51 #define GPDMA_STAT_LINK_LIST_DONE0 (1UL << 1) // Channel0 link list fetch done status
52 #define GPDMA_STAT_PHRL_END_OF_XFER0 (1UL << 2) // Channel0 transfer done status
53 #define GPDMA_STAT_GPDMAC_ERROR0 (1UL << 3) // Channel0 Transfer size/burst size /h size mismatch/flow ctrl err status
54 #define GPDMA_STAT_HRESP_ERROR1 (1UL << 4) // Channel1 dma error
55 #define GPDMA_STAT_LINK_LIST_DONE1 (1UL << 5) // Channel1 link list fetch done status
56 #define GPDMA_STAT_PHRL_END_OF_XFER1 (1UL << 6) // Channel1 transfer done status
57 #define GPDMA_STAT_GPDMAC_ERROR1 (1UL << 7) // Channel1 Transfer size/burst size /h size mismatch/flow ctrl err status
58 #define GPDMA_STAT_HRESP_ERROR2 (1UL << 8) // Channel2 dma error
59 #define GPDMA_STAT_LINK_LIST_DONE2 (1UL << 9) // Channel2 link list fetch done status
60 #define GPDMA_STAT_PHRL_END_OF_XFER2 (1UL << 10) // Channel2 transfer done status
61 #define GPDMA_STAT_GPDMAC_ERROR2 (1UL << 11) // Channel2 Transfer size/burst size /h size mismatch/flow ctrl err status
62 #define GPDMA_STAT_HRESP_ERROR3 (1UL << 12) // Channel3 dma error
63 #define GPDMA_STAT_LINK_LIST_DONE3 (1UL << 13) // Channel3 link list fetch done status
64 #define GPDMA_STAT_PHRL_END_OF_XFER3 (1UL << 14) // Channel3 transfer done status
65 #define GPDMA_STAT_GPDMAC_ERROR3 (1UL << 15) // Channel3 Transfer size/burst size /h size mismatch/flow ctrl err status
66 #define GPDMA_STAT_HRESP_ERROR4 (1UL << 16) // Channel4 dma error
67 #define GPDMA_STAT_LINK_LIST_DONE4 (1UL << 17) // Channel4 link list fetch done status
68 #define GPDMA_STAT_PHRL_END_OF_XFER4 (1UL << 18) // Channel4 transfer done status
69 #define GPDMA_STAT_GPDMAC_ERROR4 (1UL << 19) // Channel4 Transfer size/burst size /h size mismatch/flow ctrl err status
70 #define GPDMA_STAT_HRESP_ERROR5 (1UL << 20) // Channel5 dma error
71 #define GPDMA_STAT_LINK_LIST_DONE5 (1UL << 21) // Channel5 link list fetch done status
72 #define GPDMA_STAT_PHRL_END_OF_XFER5 (1UL << 22) // Channel5 transfer done status
73 #define GPDMA_STAT_GPDMAC_ERROR5 (1UL << 23) // Channel5 Transfer size/burst size /h size mismatch/flow ctrl err status
74 #define GPDMA_STAT_HRESP_ERROR6 (1UL << 24) // Channel6 dma error
75 #define GPDMA_STAT_LINK_LIST_DONE6 (1UL << 25) // Channel6 link list fetch done status
76 #define GPDMA_STAT_PHRL_END_OF_XFER6 (1UL << 26) // Channel6 transfer done status
77 #define GPDMA_STAT_GPDMAC_ERROR6 (1UL << 27) // Channel6 Transfer size/burst size /h size mismatch/flow ctrl err status
78 #define GPDMA_STAT_HRESP_ERROR7 (1UL << 28) // Channel7 dma error
79 #define GPDMA_STAT_LINK_LIST_DONE7 (1UL << 29) // Channel7 link list fetch done status
80 #define GPDMA_STAT_PHRL_END_OF_XFER7 (1UL << 30) // Channel7 transfer done status
81 #define GPDMA_STAT_GPDMAC_ERROR7 (1UL << 31) // Channel7 Transfer size/burst size /h size mismatch/flow ctrl err status
82
83 // GPDMA Event Flags
84 #define RSI_GPDMA_EVENT_HRESP_ERROR0 1
85 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE0 2
86 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER0 3
87 #define RSI_GPDMA_EVENT_GPDMAC_ERROR0 4
88 #define RSI_GPDMA_EVENT_HRESP_ERROR1 5
89 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE1 6
90 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER1 7
91 #define RSI_GPDMA_EVENT_GPDMAC_ERROR1 8
92 #define RSI_GPDMA_EVENT_HRESP_ERROR2 9
93 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE2 10
94 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER2 11
95 #define RSI_GPDMA_EVENT_GPDMAC_ERROR2 12
96 #define RSI_GPDMA_EVENT_HRESP_ERROR3 13
97 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE3 14
98 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER3 15
99 #define RSI_GPDMA_EVENT_GPDMAC_ERROR3 16
100 #define RSI_GPDMA_EVENT_HRESP_ERROR4 17
101 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE4 18
102 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER4 19
103 #define RSI_GPDMA_EVENT_GPDMAC_ERROR4 20
104 #define RSI_GPDMA_EVENT_HRESP_ERROR5 21
105 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE5 22
106 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER5 23
107 #define RSI_GPDMA_EVENT_GPDMAC_ERROR5 24
108 #define RSI_GPDMA_EVENT_HRESP_ERROR6 25
109 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE6 26
110 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER6 27
111 #define RSI_GPDMA_EVENT_GPDMAC_ERROR6 28
112 #define RSI_GPDMA_EVENT_HRESP_ERROR7 29
113 #define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE7 30
114 #define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER7 31
115 #define RSI_GPDMA_EVENT_GPDMAC_ERROR7 32
116
117 #define MEMORY_MEMORY 0x0
118 #define MEMORY_PERIPHERAL 0x1
119 #define PERIPHERAL_MEMORY 0x2
120 #define PERIPHERAL_PERIPHERAL 0x3
121
122 #define DMA_FLW_CTRL 0x0
123 #define SRC_PERI_CTRL 0x1
124 #define DST_PERI_CTRL 0x2
125 #define SRC_DST_PERI_CTRL 0x3
126
127 #define MASTER0_FETCH_IFSEL 0x0
128 #define MASTER1_FETCH_IFSEL 0x1
129
130 #define MASTER0_SEND_IFSEL 0x0
131 #define MASTER1_SEND_IFSEL 0x1
132
133 #define SRC_8_DATA_WIDTH 0x0
134 #define SRC_16_DATA_WIDTH 0x1
135 #define SRC_32_DATA_WIDTH 0x2
136
137 #define DST_8_DATA_WIDTH 0x0
138 #define DST_16_DATA_WIDTH 0x1
139 #define DST_32_DATA_WIDTH 0x2
140
141 #define LINK_LIST_EN 0x1
142 #define LINK_LIST_DIS 0x0
143 #define LINK_MASTER_0_FTCH 0x0
144 #define LINK_MASTER_1_FTCH 0x1
145
146 #define SRC_ADR_CONTIG_EN 0x1
147 #define SRC_ADR_CONTIG_DIS 0x0
148 #define DST_ADR_CONTIG_EN 0x1
149 #define DST_ADR_CONTIG_DIS 0x0
150
151 #define RETRY_ON_ERR_EN 0x1
152 #define RETRY_ON_ERR_DIS 0x0
153
154 #define SRC_FIFO_EN 0x1
155 #define SRC_FIFO_DIS 0x0
156
157 #define DST_FIFO_EN 0x1
158 #define DST_FIFO_DIS 0x0
159
160 #define MAX_TRANS_SIZE 4096
161
162 #define AHBBURST_SIZE_1 0x0
163 #define AHBBURST_SIZE_4 0x1
164 #define AHBBURST_SIZE_8 0x2
165 #define AHBBURST_SIZE_16 0x3
166 #define AHBBURST_SIZE_20 0x4
167 #define AHBBURST_SIZE_24 0x5
168 #define AHBBURST_SIZE_28 0x6
169 #define AHBBURST_SIZE_32 0x7
170
171 #define AHBBURST_SIZE_MAX 0x7
172 #define AHBBURST_SIZE_MIN 0x0
173
174 #define DST_BURST_SIZE_64 0x0
175 #define DST_BURST_SIZE_1 0x1
176 #define DST_BURST_SIZE_2 0x2
177 #define DST_BURST_SIZE_3 0x3
178 #define DST_BURST_SIZE_4 0x4
179 #define DST_BURST_SIZE_5 0x5
180 #define DST_BURST_SIZE_6 0x6
181 #define DST_BURST_SIZE_7 0x7
182 #define DST_BURST_SIZE_8 0x8
183 #define DST_BURST_SIZE_9 0x9
184 #define DST_BURST_SIZE_10 0x10
185 #define DST_BURST_SIZE_11 0x11
186 #define DST_BURST_SIZE_12 0x12
187 #define DST_BURST_SIZE_13 0x13
188 #define DST_BURST_SIZE_14 0x14
189 #define DST_BURST_SIZE_15 0x15
190 #define DST_BURST_SIZE_16 0x16
191 #define DST_BURST_SIZE_17 0x17
192 #define DST_BURST_SIZE_18 0x18
193 #define DST_BURST_SIZE_MIN 0x0
194 #define DST_BURST_SIZE_MAX 63
195
196 #define SRC_BURST_SIZE_64 0x0
197 #define SRC_BURST_SIZE_1 0x1
198 #define SRC_BURST_SIZE_2 0x2
199 #define SRC_BURST_SIZE_3 0x3
200 #define SRC_BURST_SIZE_4 0x4
201 #define SRC_BURST_SIZE_5 0x5
202 #define SRC_BURST_SIZE_6 0x6
203 #define SRC_BURST_SIZE_7 0x7
204 #define SRC_BURST_SIZE_8 0x8
205 #define SRC_BURST_SIZE_9 0x9
206 #define SRC_BURST_SIZE_10 0x10
207 #define SRC_BURST_SIZE_11 0x11
208 #define SRC_BURST_SIZE_12 0x12
209 #define SRC_BURST_SIZE_13 0x13
210 #define SRC_BURST_SIZE_14 0x14
211 #define SRC_BURST_SIZE_15 0x15
212 #define SRC_BURST_SIZE_16 0x16
213 #define SRC_BURST_SIZE_17 0x17
214 #define SRC_BURST_SIZE_18 0x18
215 #define SRC_BURST_SIZE_MIN 0x0
216 #define SRC_BURST_SIZE_MAX 63
217
218 #define DST_CHNL_ID_MIN 0x0
219 #define DST_CHNL_ID_MAX 47
220 #define SRC_CHNL_ID_MIN 0x0
221 #define SRC_CHNL_ID_MAX 47
222 #define DMA_PROT_EN 0x1
223 #define DMA_PROT_DIS 0x0
224 #define MEM_FILL_EN 0x1
225 #define MEM_FILL_DIS 0x0
226 #define MEM_FILL_ONE 0x1
227 #define MEM_FILL_ZERO 0x0
228 #define SRC_ALIGN_DIS 0x0
229 #define SRC_ALIGN_EN 0x1
230
231 #define LINK_INTR_DIS 0x0
232 #define LINK_INTR_ON 0x1
233 #define DESC_FETCH_DONE_INTR 0
234 #define TRANS_DONE_INTR 1
235
236 #define UNMASK_DESC_FETCH_INTR 0x0000FF
237 #define GPDMA_CHNL0 0
238 #define GPDMA_CHNL1 1
239 #define GPDMA_CHNL7 7
240
241 #define GPDMA_CHNL_0 0
242 #define GPDMA_CHNL_1 1
243 #define GPDMA_CHNL_2 2
244 #define GPDMA_CHNL_3 3
245
246 #define XFER_SIZE_4K 4096
247
248 #define AHB_BURST_1 0x0
249 #define AHB_BURST_4 0x1
250 #define AHB_BURST_8 0x2
251 #define AHB_BURST_16 0x3
252 #define AHB_BURST_20 0x4
253 #define AHB_BURST_24 0x5
254 #define AHB_BURST_28 0x6
255 #define AHB_BURST_32 0x7
256
257 #define SRC_BURST_64 0x00
258 #define SRC_BURST_1 0x01
259 #define SRC_BURST_16 0x10
260 #define SRC_BURST_63 0x3F
261
262 #define DST_BURST_64 0x00
263 #define DST_BURST_1 0x01
264 #define DST_BURST_16 0x10
265 #define DST_BURST_63 0x3F
266
267 #define FILL_ZEROS 0x0
268 #define FILL_ONES 0x1
269
270 #define PRIO_LEVEL_4 0x3
271 #define PRIO_LEVEL_3 0x2
272 #define PRIO_LEVEL_2 0x1
273 #define PRIO_LEVEL_1 0x0
274
275 #define MAX_CHANNELS 0x8
276
277 #define DESC_COUNT 4
278 #define DESC_INDEX0 0
279 #define DESC_INDEX1 1
280 #define DESC_INDEX2 2
281 #define DESC_INDEX3 3
282
283 #define FIFO_SIZE_MAX 512
284
285 #define NO_DST_CHNL_ID 0x0
286 #define NO_SRC_CHNL_ID 0x0
287
288 #define HRESP_ERR 0
289 #define GPDMAC_ERR 1
290
291 #define M4SS_GPDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x04)))
292 #define CLOCK_BASE 0x46000000
293 #define CLK_ENABLE_SET_2_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x08)))
294 #define CLK_ENABLE_SET_1_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x00)))
295
296 typedef GPDMA_G_Type RSI_GPDMAG_T;
297 typedef GPDMA_C_Type RSI_GPDMAC_T;
298
299 // GPDMA Error flags
300 #define HRESP_ERR0 (1UL << 0)
301 #define HRESP_ERR1 (1UL << 4)
302 #define HRESP_ERR2 (1UL << 8)
303 #define HRESP_ERR3 (1UL << 12)
304 #define HRESP_ERR4 (1UL << 16)
305 #define HRESP_ERR5 (1UL << 20)
306 #define HRESP_ERR6 (1UL << 24)
307 #define HRESP_ERR7 (1UL << 28)
308 #define GPDMAC_ERR0 (1UL << 3)
309 #define GPDMAC_ERR1 (1UL << 7)
310 #define GPDMAC_ERR2 (1UL << 11)
311 #define GPDMAC_ERR3 (1UL << 15)
312 #define GPDMAC_ERR4 (1UL << 19)
313 #define GPDMAC_ERR5 (1UL << 23)
314 #define GPDMAC_ERR6 (1UL << 27)
315 #define GPDMAC_ERR7 (1UL << 31)
316
317 // GPDMA transfer status flags
318 #define LINK_LIST_DONE0 (1UL << 1)
319 #define PHRL_END_OF_TFR0 (1UL << 2)
320 #define LINK_LIST_DONE1 (1UL << 5)
321 #define PHRL_END_OF_TFR1 (1UL << 6)
322 #define LINK_LIST_DONE2 (1UL << 9)
323 #define PHRL_END_OF_TFR2 (1UL << 10)
324 #define LINK_LIST_DONE3 (1UL << 13)
325 #define PHRL_END_OF_TFR3 (1UL << 14)
326 #define LINK_LIST_DONE04 (1UL << 17)
327 #define PHRL_END_OF_TFR4 (1UL << 18)
328 #define LINK_LIST_DONE5 (1UL << 21)
329 #define PHRL_END_OF_TFR5 (1UL << 22)
330 #define LINK_LIST_DONE6 (1UL << 25)
331 #define PHRL_END_OF_TFR6 (1UL << 26)
332 #define LINK_LIST_DONE7 (1UL << 29)
333 #define PHRL_END_OF_TFR7 (1UL << 30)
334
335 // brief GPDMA Driver Capabilities.
336 typedef struct {
337 unsigned int noOfChannels : 4; // Total supporting channels
338 unsigned int noOfMasterInterfaces : 2; // No of master interfaces supported
339 unsigned int noOfPeriSupport : 7; // total supporting peripherals
340 unsigned int noOfPriorityLevels : 3; // No of priority levels
341
342 } RSI_GPDMA_CAPABILITIES_T;
343
344 // brief GPDMA Descriptor parameters.
345
346 // brief chnl_ctrl_info
347 typedef PRE_PACK struct POST_PACK {
348 unsigned int transSize : 12; // Transfer lenght in bytes
349 unsigned int transType : 2; // Type of DMA transfer
350 unsigned int dmaFlwCtrl : 2; // Flow control type
351 unsigned int mastrIfFetchSel : 1; // Master controller select to fetch data
352 unsigned int mastrIfSendSel : 1; // Master controller select to send data
353 unsigned int destDataWidth : 2; // Destination data width
354 unsigned int srcDataWidth : 2; // Source data width
355 unsigned int srcAlign : 1; // Source Alignment
356 unsigned int linkListOn : 1; // Linked transfer on
357 unsigned int linkListMstrSel : 1; // Master controller select for link transfers
358 unsigned int srcAddContiguous : 1; // Source address contiguous
359 unsigned int dstAddContiguous : 1; // Destination address contiguous
360 unsigned int retryOnErr : 1; // Retry on error
361 unsigned int linkInterrupt : 1; // Link interrupt enable
362 unsigned int srcFifoMode : 1; // Source FIFO mode
363 unsigned int dstFifoMode : 1; // Destination FIFO mode
364 unsigned int reserved : 1;
365 } RSI_GPDMA_CHA_CONTROL_T;
366
367 //brief Misc_chnl_ctrl_info
368 typedef PRE_PACK struct POST_PACK {
369 unsigned int ahbBurstSize : 3; // AHB Burst size
370 unsigned int destDataBurst : 6; // Destination data Burst size
371 unsigned int srcDataBurst : 6; // source data Burst size
372 unsigned int destChannelId : 6; // Dest channel ID
373 unsigned int srcChannelId : 6; // Source channel ID
374 unsigned int dmaProt : 3;
375 unsigned int memoryFillEn : 1; // Memory fill enable
376 unsigned int memoryOneFill : 1; // Memory fill with 1 or 0
377 } RSI_GPDMA_MISC_CHA_CONTROL_T;
378
379 //brief GPDMA controller handle type
380 typedef void *RSI_GPDMA_HANDLE_T;
381
382 typedef PRE_PACK struct POST_PACK {
383 uint32_t *pNextLink; // Pointer to next descriptor link in a chain, NULL to end
384 void *src; // source address
385 void *dest; // destination address
386 RSI_GPDMA_CHA_CONTROL_T chnlCtrlConfig; // Channel control register paramter
387 RSI_GPDMA_MISC_CHA_CONTROL_T miscChnlCtrlConfig; // Channel control register paramter
388 } RSI_GPDMA_DESC_T;
389
390 typedef void (*gpdmaTransferCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh);
391 typedef void (*gpdmaTransferDescFetchCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle,
392 RSI_GPDMA_DESC_T *pTranDesc,
393 uint32_t dmaCh);
394 typedef void (*gpdmaTransferHrespErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh);
395 typedef void (*gpdmaTransferRpdmacErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh);
396 typedef void (*gpdmaTransferErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh);
397
398 // @brief GPDMA controller callback IDs
399 typedef enum {
400 RSI_GPDMA_XFERCOMPLETE_CB = 0, // Callback ID for GPDMA transfer descriptor chain complete
401 RSI_GPDMA_XFERDESCFETCHCOMPLETE_CB, // Callback ID for GPDMA transfer descriptor complete
402 RSI_GPDMA_XFERHRESPERROR_CB, // Callback ID for GPDMA transfer error occurance
403 RSI_GPDMA_XFERGPDMACERROR_CB
404 } RSI_GPDMA_CALLBACK_T;
405
406 // Private data structure used for the GPDMA controller driver, holds the driver and peripheral context
407 typedef struct {
408 void *pUserData; // Pointer to user data used by driver instance, use NULL if not used
409 RSI_GPDMAG_T *baseG; // GPDMA global registers base
410 RSI_GPDMAC_T *baseC; // GPDMA channel specific registers base
411 RSI_GPDMA_DESC_T *sramBase; // SRAM descriptor table (all channels)
412 gpdmaTransferCompleteCB gpdmaCompCB; // Transfer descriptor chain completion callback
413 gpdmaTransferDescFetchCompleteCB gpdmaDescFetchCompCB; // Transfer descriptor fetch completion callback
414 gpdmaTransferHrespErrorCB gpdmaHrespErrorCB; // Transfer error callback
415 gpdmaTransferRpdmacErrorCB gpdmaRpdmacErrorCB; // Transfer error callback
416 uint32_t dmaCh; // GPDMA channel
417 } GPDMA_DATACONTEXT_T;
418
419 // GPDMA Init structure
420 typedef PRE_PACK struct POST_PACK {
421 void *pUserData; // Pointer to user data used by driver instance, use NULL if not used
422 uint32_t baseG; // Pointer to GPDMA global register instance
423 uint32_t baseC; // Pointer to GPDMA channel specific register instance
424 uint32_t sramBase; // Pointer to memory used for GPDMA descriptor storage, must be 512 byte aligned
425 } RSI_GPDMA_INIT_T;
426
427 // brief GPDMA transfer channel setup structure (use this structure as const if possible)
428 typedef PRE_PACK struct POST_PACK {
429 uint32_t channelPrio; // Channel priority level
430 uint32_t descFetchDoneIntr; // Desc fetch done interrupt flag
431 uint32_t xferDoneIntr; // Transfer done interrupt flag
432 uint32_t hrespErr; // dma error flag
433 uint32_t gpdmacErr; // Transfer size/burst size /h size mismatch/flow ctrl err
434 uint32_t dmaCh; // Channel number
435 } RSI_GPDMA_CHA_CFG_T;
436
437 /*===================================================*/
438 /**
439 * @fn void RSI_GPDMA_FIFOConfig( RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh,
440 uint32_t startAdr, uint32_t size )
441 * @brief Set fifo configuration for data transmission.
442 * @param[in] pHandle : Pointer to driver context handle
443 * @param[in] dmaCh : DMA channel number(0-7)
444 * @param[in] startAdr : starting address for data transfer.
445 * @param[in] size : size of data transfer.
446 * @return none.
447 */
RSI_GPDMA_FIFOConfig(RSI_GPDMA_HANDLE_T pHandle,uint8_t dmaCh,uint32_t startAdr,uint32_t size)448 STATIC INLINE void RSI_GPDMA_FIFOConfig(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, uint32_t startAdr, uint32_t size)
449 {
450 GPDMA_DATACONTEXT_T *pDrv = (GPDMA_DATACONTEXT_T *)pHandle;
451 pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_STRT_ADDR = (unsigned int)(startAdr & 0x3F);
452 pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_SIZE = (unsigned int)(size & 0x3F);
453 }
454
455 // FUNCTION PROTOTYPES
456 RSI_DRIVER_VERSION_M4 RSI_GPDMA_GetVersion(void);
457
458 RSI_GPDMA_CAPABILITIES_T RSI_GPDMA_GetCapabilities(void);
459
460 uint32_t gpdma_get_mem_size(void);
461
462 RSI_GPDMA_HANDLE_T gpdma_init(void *mem, const RSI_GPDMA_INIT_T *pInit);
463
464 void gpdma_register_callback(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB);
465
466 rsi_error_t gpdma_abort_channel(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh);
467
468 rsi_error_t gpdma_setup_channel(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
469
470 rsi_error_t gpdma_build_descriptors(RSI_GPDMA_HANDLE_T pHandle,
471 RSI_GPDMA_DESC_T *pXferCfg,
472 RSI_GPDMA_DESC_T *pDesc,
473 RSI_GPDMA_DESC_T *pDescPrev);
474
475 rsi_error_t gpdma_setup_channelTransfer(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc);
476
477 void gpdma_interrupt_handler(RSI_GPDMA_HANDLE_T pHandle);
478
479 void gpdma_deInit(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
480
481 rsi_error_t gpdma_dma_channel_trigger(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh);
482
483 uint32_t gpdma_channel_is_enabled(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh);
484
485 rsi_error_t gpdma_interrupt_disable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
486
487 rsi_error_t gpdma_interrupt_enable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
488
489 rsi_error_t gpdma_error_status_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
490
491 uint32_t gpdma_get_error_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
492
493 rsi_error_t gpdma_interrupt_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
494
495 uint32_t gpdma_interrupt_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg);
496
497 uint8_t RSI_GPDMA_GetChannelActivity(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh);
498
499 #ifdef __cplusplus
500 }
501 #endif
502 #endif //RSI_GPDMA_H
503
