1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_NVIC_H 9 #define _HARDWARE_STRUCTS_NVIC_H 10 11 /** 12 * \file rp2350/nvic.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/m33.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/m33.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 #if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV 27 #error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" 28 #endif 29 30 typedef struct { 31 // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) 32 _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 33 // Enables or reads the enabled state of each group of 32 interrupts 34 // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... 35 io_rw_32 iser[2]; 36 37 uint32_t _pad0[30]; 38 39 // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) 40 _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 41 // Clears or reads the enabled state of each group of 32 interrupts 42 // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... 43 io_rw_32 icer[2]; 44 45 uint32_t _pad1[30]; 46 47 // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) 48 _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 49 // Enables or reads the pending state of each group of 32 interrupts 50 // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... 51 io_rw_32 ispr[2]; 52 53 uint32_t _pad2[30]; 54 55 // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) 56 _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 57 // Clears or reads the pending state of each group of 32 interrupts 58 // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... 59 io_rw_32 icpr[2]; 60 61 uint32_t _pad3[30]; 62 63 // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) 64 _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 65 // For each group of 32 interrupts, shows the active state of each interrupt 66 // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... 67 io_rw_32 iabr[2]; 68 69 uint32_t _pad4[30]; 70 71 // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) 72 _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 73 // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state 74 // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... 75 io_rw_32 itns[2]; 76 77 uint32_t _pad5[30]; 78 79 // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) 80 _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 81 // Sets or reads interrupt priorities 82 // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... 83 // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... 84 // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... 85 // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... 86 io_rw_32 ipr[16]; 87 } nvic_hw_t; 88 89 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) 90 #define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET)) 91 static_assert(sizeof (nvic_hw_t) == 0x0340, ""); 92 93 #endif // _HARDWARE_STRUCTS_NVIC_H 94 95
