1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_MPU_H 9 #define _HARDWARE_STRUCTS_MPU_H 10 11 /** 12 * \file rp2040/mpu.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/m0plus.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE 28 // MPU Type Register 29 // 0x00ff0000 [23:16] IREGION (0x00) Instruction region 30 // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU 31 // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps 32 io_ro_32 type; 33 34 _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL 35 // MPU Control Register 36 // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... 37 // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs 38 // 0x00000001 [0] ENABLE (0) Enables the MPU 39 io_rw_32 ctrl; 40 41 _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR 42 // MPU Region Number Register 43 // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... 44 io_rw_32 rnr; 45 46 _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR 47 // MPU Region Base Address Register 48 // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region 49 // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... 50 // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... 51 io_rw_32 rbar; 52 53 _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR 54 // MPU Region Attribute and Size Register 55 // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field 56 // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable 57 // 0x0000003e [5:1] SIZE (0x00) Indicates the region size 58 // 0x00000001 [0] ENABLE (0) Enables the region 59 io_rw_32 rasr; 60 } mpu_hw_t; 61 62 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) 63 static_assert(sizeof (mpu_hw_t) == 0x0014, ""); 64 65 #endif // _HARDWARE_STRUCTS_MPU_H 66 67
