1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _DREQ_H 9 #define _DREQ_H 10 11 /** 12 * \file rp2040/dreq.h 13 */ 14 15 #ifdef __ASSEMBLER__ 16 #define DREQ_PIO0_TX0 0 17 #define DREQ_PIO0_TX1 1 18 #define DREQ_PIO0_TX2 2 19 #define DREQ_PIO0_TX3 3 20 #define DREQ_PIO0_RX0 4 21 #define DREQ_PIO0_RX1 5 22 #define DREQ_PIO0_RX2 6 23 #define DREQ_PIO0_RX3 7 24 #define DREQ_PIO1_TX0 8 25 #define DREQ_PIO1_TX1 9 26 #define DREQ_PIO1_TX2 10 27 #define DREQ_PIO1_TX3 11 28 #define DREQ_PIO1_RX0 12 29 #define DREQ_PIO1_RX1 13 30 #define DREQ_PIO1_RX2 14 31 #define DREQ_PIO1_RX3 15 32 #define DREQ_SPI0_TX 16 33 #define DREQ_SPI0_RX 17 34 #define DREQ_SPI1_TX 18 35 #define DREQ_SPI1_RX 19 36 #define DREQ_UART0_TX 20 37 #define DREQ_UART0_RX 21 38 #define DREQ_UART1_TX 22 39 #define DREQ_UART1_RX 23 40 #define DREQ_PWM_WRAP0 24 41 #define DREQ_PWM_WRAP1 25 42 #define DREQ_PWM_WRAP2 26 43 #define DREQ_PWM_WRAP3 27 44 #define DREQ_PWM_WRAP4 28 45 #define DREQ_PWM_WRAP5 29 46 #define DREQ_PWM_WRAP6 30 47 #define DREQ_PWM_WRAP7 31 48 #define DREQ_I2C0_TX 32 49 #define DREQ_I2C0_RX 33 50 #define DREQ_I2C1_TX 34 51 #define DREQ_I2C1_RX 35 52 #define DREQ_ADC 36 53 #define DREQ_XIP_STREAM 37 54 #define DREQ_XIP_SSITX 38 55 #define DREQ_XIP_SSIRX 39 56 #define DREQ_DMA_TIMER0 59 57 #define DREQ_DMA_TIMER1 60 58 #define DREQ_DMA_TIMER2 61 59 #define DREQ_DMA_TIMER3 62 60 #define DREQ_FORCE 63 61 #else 62 /** 63 * \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t) 64 * \ingroup hardware_dma 65 */ 66 typedef enum dreq_num_rp2040 { 67 DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ 68 DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ 69 DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ 70 DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ 71 DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ 72 DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ 73 DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ 74 DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ 75 DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ 76 DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ 77 DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ 78 DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ 79 DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ 80 DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ 81 DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ 82 DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ 83 DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ 84 DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ 85 DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ 86 DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ 87 DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ 88 DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ 89 DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ 90 DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ 91 DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ 92 DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ 93 DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ 94 DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ 95 DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ 96 DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ 97 DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ 98 DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ 99 DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ 100 DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ 101 DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ 102 DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ 103 DREQ_ADC = 36, ///< Select the ADC as DREQ 104 DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ 105 DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ 106 DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ 107 DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ 108 DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ 109 DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ 110 DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ 111 DREQ_FORCE = 63, ///< Select FORCE as DREQ 112 DREQ_COUNT 113 } dreq_num_t; 114 #endif 115 116 #endif // _DREQ_H 117 118
