1 /* 2 * SPDX-FileCopyrightText: 2016 Cesanta Software Limited 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 * 6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD 7 */ 8 9 /* ROM function prototypes for functions in ROM which are 10 called by the flasher stubs. 11 */ 12 #pragma once 13 14 #include <stdint.h> 15 #include "soc_support.h" 16 17 int uart_rx_one_char(uint8_t *ch); 18 uint8_t uart_rx_one_char_block(); 19 int uart_tx_one_char(char ch); 20 21 #if ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4 22 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */ 23 int uart_tx_one_char2(char ch); 24 #define uart_tx_one_char(ch) uart_tx_one_char2(ch) 25 #endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4 26 27 void uart_div_modify(uint32_t uart_no, uint32_t baud_div); 28 29 void ets_delay_us(uint32_t us); 30 31 typedef enum { SPI_FLASH_RESULT_OK = 0, 32 SPI_FLASH_RESULT_ERR = 1, 33 SPI_FLASH_RESULT_TIMEOUT = 2 } SpiFlashOpResult; 34 35 SpiFlashOpResult SPILock(); 36 SpiFlashOpResult SPIUnlock(); 37 SpiFlashOpResult SPIRead(uint32_t addr, void *dst, uint32_t size); 38 SpiFlashOpResult SPIWrite(uint32_t addr, const uint8_t *src, uint32_t size); 39 SpiFlashOpResult SPIEraseChip(); 40 SpiFlashOpResult SPIEraseBlock(uint32_t block_num); 41 SpiFlashOpResult SPIEraseSector(uint32_t sector_num); 42 uint32_t SPI_read_status(); 43 uint32_t Wait_SPI_Idle(); 44 void spi_flash_attach(); 45 46 void SelectSpiFunction(); 47 uint32_t SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 48 49 void ets_isr_mask(uint32_t ints); 50 void ets_isr_unmask(uint32_t ints); 51 void ets_set_user_start(void (*user_start_fn)()); 52 53 void software_reset(); 54 void software_reset_cpu(int cpu_no); 55 56 #ifdef ESP32C2 // ESP32C2 ROM uses mbedtls_md5 57 struct MD5Context { // Called mbedtls_md5_context in ROM 58 uint32_t total[2]; // number of bytes processed 59 uint32_t state[4]; // intermediate digest state 60 unsigned char buffer[64]; // data block being processed 61 }; 62 63 int mbedtls_md5_starts_ret(struct MD5Context *ctx); 64 int mbedtls_md5_update_ret(struct MD5Context *ctx, const unsigned char *input, size_t ilen); 65 int mbedtls_md5_finish_ret(struct MD5Context *ctx, unsigned char digest[16]); 66 67 #define MD5Init(ctx) mbedtls_md5_starts_ret(ctx) 68 #define MD5Update(ctx, buf, n) mbedtls_md5_update_ret(ctx, buf, n) 69 #define MD5Final(digest, ctx) mbedtls_md5_finish_ret(ctx, digest) 70 #else // not ESP32C2 71 struct MD5Context { 72 uint32_t buf[4]; 73 uint32_t bits[2]; 74 uint8_t in[64]; 75 }; 76 77 void MD5Init(struct MD5Context *ctx); 78 void MD5Update(struct MD5Context *ctx, void *buf, uint32_t len); 79 void MD5Final(uint8_t digest[16], struct MD5Context *ctx); 80 #endif // not ESP32C2 81 82 typedef struct { 83 uint32_t device_id; 84 uint32_t chip_size; // chip size in bytes 85 uint32_t block_size; 86 uint32_t sector_size; 87 uint32_t page_size; 88 uint32_t status_mask; 89 } esp_rom_spiflash_chip_t; 90 91 92 typedef void (*int_handler_t)(void *arg); 93 int_handler_t ets_isr_attach(uint32_t int_num, int_handler_t handler, 94 void *arg); 95 /* Some ESP32-onwards ROM functions */ 96 #if ESP32_OR_LATER 97 void uart_tx_flush(int uart); 98 uint32_t ets_efuse_get_spiconfig(void); 99 100 #if ESP32 101 SpiFlashOpResult esp_rom_spiflash_write_encrypted(uint32_t addr, const uint8_t *src, uint32_t size); 102 #else 103 void SPI_Write_Encrypt_Enable(); 104 void SPI_Write_Encrypt_Disable(); 105 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len); 106 #endif 107 108 #if ESP32S2_OR_LATER 109 uint32_t GetSecurityInfoProc(int* pMsg, int* pnErr, uint8_t *buf); // pMsg and pnErr unused in ROM 110 #if ESP32C3 111 extern uint32_t _rom_eco_version; // rom constant to define ECO version 112 uint32_t GetSecurityInfoProcNewEco(int* pMsg, int* pnErr, uint8_t *buf); // GetSecurityInfo for C3 ECO7+ 113 #endif // ESP32C3 114 SpiFlashOpResult SPI_read_status_high(esp_rom_spiflash_chip_t *spi, uint32_t *status); 115 #else 116 /* Note: On ESP32 this was a static function whose first argument was elided by the 117 compiler. */ 118 SpiFlashOpResult SPI_read_status_high(uint32_t *status); 119 #endif 120 121 SpiFlashOpResult SPI_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 122 123 void intr_matrix_set(int cpu_no, uint32_t module_num, uint32_t intr_num); 124 #endif /* ESP32_OR_LATER */ 125 126 /* RISC-V-only ROM functions */ 127 #if IS_RISCV 128 void esprv_intc_int_set_priority(int intr_num, int priority); 129 #endif // IS_RISCV 130 131 /* USB-OTG and USB-JTAG-Serial imports */ 132 #ifdef WITH_USB_OTG 133 #define ACM_BYTES_PER_TX 64 134 #define ACM_STATUS_LINESTATE_CHANGED -1 135 #define ACM_STATUS_RX -4 136 #define LINE_CTRL_BAUD_RATE (1 << 0) 137 #define LINE_CTRL_RTS (1 << 1) 138 #define LINE_CTRL_DTR (1 << 2) 139 #define LINE_CTRL_DCD (1 << 3) 140 #define LINE_CTRL_DSR (1 << 4) 141 #define USBDC_PERSIST_ENA (1<<31) 142 void usb_dw_isr_handler(void* arg); 143 typedef void cdc_acm_device; 144 extern cdc_acm_device *uart_acm_dev; 145 typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); 146 void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb); 147 void cdc_acm_irq_rx_enable(cdc_acm_device *dev); 148 void cdc_acm_irq_rx_disable(cdc_acm_device *dev); 149 int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size); 150 int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len); 151 int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val); 152 int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); 153 void cdc_acm_irq_state_enable(cdc_acm_device *dev); 154 void usb_dc_check_poll_for_interrupts(void); 155 void chip_usb_set_persist_flags(uint32_t flags); 156 int usb_dc_prepare_persist(void); 157 #endif // WITH_USB_OTG 158 159 #if WITH_USB_JTAG_SERIAL || WITH_USB_OTG 160 typedef struct { 161 uint8_t *pRcvMsgBuff; 162 uint8_t *pWritePos; 163 uint8_t *pReadPos; 164 uint8_t TrigLvl; 165 int BuffState; 166 } RcvMsgBuff; 167 168 typedef struct { 169 int baud_rate; 170 int data_bits; 171 int exist_parity; 172 int parity; 173 int stop_bits; 174 int flow_ctrl; 175 uint8_t buff_uart_no; 176 RcvMsgBuff rcv_buff; 177 int rcv_state; 178 int received; 179 } UartDevice; 180 181 UartDevice * GetUartDevice(); 182 #endif // WITH_USB_JTAG_SERIAL || WITH_USB_OTG 183 184 #if defined(ESP32S3) 185 #define BIT(nr) (1UL << (nr)) 186 #define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) 187 188 typedef enum { 189 SPI_FLASH_QIO_MODE = 0, 190 SPI_FLASH_QOUT_MODE, 191 SPI_FLASH_DIO_MODE, 192 SPI_FLASH_DOUT_MODE, 193 SPI_FLASH_FASTRD_MODE, 194 SPI_FLASH_SLOWRD_MODE, 195 SPI_FLASH_OPI_STR_MODE, 196 SPI_FLASH_OPI_DTR_MODE, 197 SPI_FLASH_OOUT_MODE, 198 SPI_FLASH_OIO_STR_MODE, 199 SPI_FLASH_OIO_DTR_MODE, 200 SPI_FLASH_QPI_MODE, 201 } SpiFlashRdMode; 202 203 typedef enum { 204 ESP_ROM_SPIFLASH_RESULT_OK, 205 ESP_ROM_SPIFLASH_RESULT_ERR, 206 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 207 } esp_rom_spiflash_result_t; 208 209 #define CMD_RDID 0x9F 210 #define CMD_RDSR 0x05 211 #define CMD_WREN 0x06 212 #define CMD_SECTOR_ERASE 0x20 213 #define CMD_SECTOR_ERASE_4B 0x21 214 #define CMD_FSTRD4B 0x0C 215 #define CMD_LARGE_BLOCK_ERASE 0xD8 216 #define CMD_LARGE_BLOCK_ERASE_4B 0xDC 217 #define CMD_PROGRAM_PAGE_4B 0x12 218 219 #define OPIFLASH_DRIVER() { \ 220 .rdid = { \ 221 .mode = SPI_FLASH_FASTRD_MODE, \ 222 .cmd_bit_len = 8, \ 223 .cmd = CMD_RDID, \ 224 .addr = 0, \ 225 .addr_bit_len = 0, \ 226 .dummy_bit_len = 0, \ 227 .data_bit_len = 24, \ 228 .cs_sel = 0x1, \ 229 .is_pe = 0, \ 230 }, \ 231 .rdsr = { \ 232 .mode = SPI_FLASH_FASTRD_MODE, \ 233 .cmd_bit_len = 8, \ 234 .cmd = CMD_RDSR, \ 235 .addr = 0, \ 236 .addr_bit_len = 0, \ 237 .dummy_bit_len = 0, \ 238 .data_bit_len = 8, \ 239 .cs_sel = 0x1, \ 240 .is_pe = 0, \ 241 }, \ 242 .wren = { \ 243 .mode = SPI_FLASH_FASTRD_MODE, \ 244 .cmd_bit_len = 8, \ 245 .cmd = CMD_WREN, \ 246 .addr = 0, \ 247 .addr_bit_len = 0, \ 248 .dummy_bit_len = 0, \ 249 .data_bit_len = 0, \ 250 .cs_sel = 0x1, \ 251 .is_pe = 0, \ 252 }, \ 253 .se = { \ 254 .mode = SPI_FLASH_FASTRD_MODE, \ 255 .cmd_bit_len = 8, \ 256 .cmd = CMD_SECTOR_ERASE_4B, \ 257 .addr = 0, \ 258 .addr_bit_len = 32, \ 259 .dummy_bit_len = 0, \ 260 .data_bit_len = 0, \ 261 .cs_sel = 0x1, \ 262 .is_pe = 1, \ 263 }, \ 264 .be64k = { \ 265 .mode = SPI_FLASH_FASTRD_MODE, \ 266 .cmd_bit_len = 8, \ 267 .cmd = CMD_LARGE_BLOCK_ERASE_4B, \ 268 .addr = 0, \ 269 .addr_bit_len = 32, \ 270 .dummy_bit_len = 0, \ 271 .data_bit_len = 0, \ 272 .cs_sel = 0x1, \ 273 .is_pe = 1, \ 274 }, \ 275 .read = { \ 276 .mode = SPI_FLASH_FASTRD_MODE, \ 277 .cmd_bit_len = 8, \ 278 .cmd = CMD_FSTRD4B, \ 279 .addr = 0, \ 280 .addr_bit_len = 32, \ 281 .dummy_bit_len = 0, \ 282 .data_bit_len = 0, \ 283 .cs_sel = 0x1, \ 284 .is_pe = 0, \ 285 }, \ 286 .pp = { \ 287 .mode = SPI_FLASH_FASTRD_MODE, \ 288 .cmd_bit_len = 8, \ 289 .cmd = CMD_PROGRAM_PAGE_4B, \ 290 .addr = 0, \ 291 .addr_bit_len = 32, \ 292 .dummy_bit_len = 0, \ 293 .data_bit_len = 0, \ 294 .cs_sel = 0x1, \ 295 .is_pe = 1, \ 296 }, \ 297 .cache_rd_cmd = { \ 298 .addr_bit_len = 32, \ 299 .dummy_bit_len = 20*2, \ 300 .cmd = CMD_FSTRD4B, \ 301 .cmd_bit_len = 16, \ 302 .var_dummy_en = 1, \ 303 } \ 304 } 305 306 #ifndef ESP32S3BETA2 307 typedef struct { 308 uint8_t mode; 309 uint8_t cmd_bit_len; 310 uint16_t cmd; 311 uint32_t addr; 312 uint8_t addr_bit_len; 313 uint8_t dummy_bit_len; 314 uint8_t data_bit_len; 315 uint8_t cs_sel: 4; 316 uint8_t is_pe: 4; 317 } esp_rom_opiflash_cmd_t; 318 319 typedef struct { 320 uint8_t addr_bit_len; 321 uint8_t dummy_bit_len; 322 uint16_t cmd; 323 uint8_t cmd_bit_len; 324 uint8_t var_dummy_en; 325 } esp_rom_opiflash_spi0rd_t; 326 327 typedef struct { 328 esp_rom_opiflash_cmd_t rdid; 329 esp_rom_opiflash_cmd_t rdsr; 330 esp_rom_opiflash_cmd_t wren; 331 esp_rom_opiflash_cmd_t se; 332 esp_rom_opiflash_cmd_t be64k; 333 esp_rom_opiflash_cmd_t read; 334 esp_rom_opiflash_cmd_t pp; 335 esp_rom_opiflash_spi0rd_t cache_rd_cmd; 336 } esp_rom_opiflash_def_t; 337 338 void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def); 339 bool ets_efuse_flash_octal_mode(void); 340 #endif //ESP32S3BETA2 341 342 void esp_rom_opiflash_exec_cmd(int spi_num, SpiFlashRdMode mode, 343 uint32_t cmd, int cmd_bit_len, 344 uint32_t addr, int addr_bit_len, 345 int dummy_bits, 346 uint8_t* mosi_data, int mosi_bit_len, 347 uint8_t* miso_data, int miso_bit_len, 348 uint32_t cs_mask, 349 bool is_write_erase_operation); 350 351 esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(); 352 esp_rom_spiflash_result_t esp_rom_opiflash_wren(); 353 esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num); 354 esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num); 355 SpiFlashOpResult SPI_write_enable(esp_rom_spiflash_chip_t *spi); 356 #endif // ESP32S3 357
