1/*
2 * Copyright (c) 2022 Intel Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <dt-bindings/pinctrl/same70q-pinctrl.h>
7
8&pinctrl {
9	afec0_default: afec0_default {	/* ADCL - J502 */
10		group1 {
11			pinmux = <PD30X_AFE0_AD0>,
12				 <PA19X_AFE0_AD8>,
13				 <PA17X_AFE0_AD6>;
14		};
15	};
16
17	can0_default: can0_default {
18		group1 {
19			pinmux = <PB3A_CAN0_RX>,
20				 <PB2A_CAN0_TX>;
21		};
22	};
23
24	gmac_rmii: gmac_rmii {
25		group1 {
26			pinmux = <PD0A_GMAC_GTXCK>,
27				 <PD1A_GMAC_GTXEN>,
28				 <PD2A_GMAC_GTX0>,
29				 <PD3A_GMAC_GTX1>,
30				 <PD4A_GMAC_GRXDV>,
31				 <PD5A_GMAC_GRX0>,
32				 <PD6A_GMAC_GRX1>,
33				 <PD7A_GMAC_GRXER>;
34		};
35	};
36
37	mdio_default: mdio_default {
38		group1 {
39			pinmux = <PD8A_GMAC_GMDC>,
40				 <PD9A_GMAC_GMDIO>;
41		};
42	};
43
44	pwm_default: pwm_default {
45		group1 {
46			pinmux = <PA0A_PWMC0_PWMH0>,
47				 <PC19B_PWMC0_PWMH2>,
48				 <PD26A_PWMC0_PWML2>;
49		};
50	};
51
52	spi0_default: spi0_default {
53		group1 {
54			pinmux = <PD20B_SPI0_MISO>,
55				 <PD21B_SPI0_MOSI>,
56				 <PD22B_SPI0_SPCK>;
57		};
58	};
59
60	spi1_default: spi1_default {
61		group1 {
62			pinmux = <PC26C_SPI1_MISO>,
63				 <PC27C_SPI1_MOSI>,
64				 <PC24C_SPI1_SPCK>,
65				 <PC25C_SPI1_NPCS0>;
66		};
67	};
68
69	ssc_default: ssc_default {
70		group1 {
71			pinmux = <PD24B_SSC_RF>,
72				 <PA22A_SSC_RK>,
73				 <PA10C_SSC_RD>,
74				 <PB0D_SSC_TF>,
75				 <PB1D_SSC_TK>,
76				 <PB5D_SSC_TD>;
77		};
78	};
79
80	tc0_qdec_default: tc0_qdec_default {
81		group1 {
82			pinmux = <PA0B_TC0_TIOA0>,
83				 <PA1B_TC0_TIOB0>;
84		};
85	};
86
87	twihs0_default: twihs0_default {
88		group1 {
89			pinmux = <PA4A_TWI0_TWCK>,
90				 <PA3A_TWI0_TWD>;
91		};
92	};
93
94	twihs1_default: twihs1_default {
95		group1 {
96			pinmux = <PB5A_TWI1_TWCK>,
97				 <PB4A_TWI1_TWD>;
98		};
99	};
100
101	twihs2_default: twihs2_default {
102		group1 {
103			pinmux = <PD28C_TWI2_TWCK>,
104				 <PD27C_TWI2_TWD>;
105		};
106	};
107
108	uart0_default: uart0_default {
109		group1 {
110			pinmux = <PA9A_UART0_RXD>,
111				<PA10A_UART0_TXD>;
112		};
113	};
114
115	uart1_default: uart1_default {
116		group1 {
117			pinmux = <PA5C_UART1_RXD>,
118				<PA6C_UART1_TXD>;
119		};
120	};
121
122	uart2_default: uart2_default {
123		group1 {
124			pinmux = <PD25C_UART2_RXD>,
125				<PD26C_UART2_TXD>;
126		};
127	};
128
129	uart3_default: uart3_default {
130		group1 {
131			pinmux = <PD28A_UART3_RXD>,
132				 <PD30A_UART3_TXD>;
133		};
134	};
135	uart4_default: uart4_default {
136		group1 {
137			pinmux = <PD19C_UART4_TXD>,
138				 <PD18C_UART4_RXD>;
139		};
140	};
141
142	usart0_default: usart0_default {
143		group1 {
144			pinmux = <PB0C_USART0_RXD>,
145				 <PB1C_USART0_TXD>;
146		};
147	};
148
149	usart0_hw_ctrl_flow_clk: usart0_hw_ctrl_flow_clk {
150		group1 {
151			pinmux = <PB0C_USART0_RXD>,
152				 <PB3C_USART0_RTS>;
153			bias-pull-up;
154		};
155		group2 {
156			pinmux = <PB1C_USART0_TXD>,
157				 <PB2C_USART0_CTS>,
158				 <PB13C_USART0_SCK>;
159		};
160	};
161
162	usart1_default: usart1_default {
163		group1 {
164			pinmux = <PA21A_USART1_RXD>,
165				 <PB4D_USART1_TXD>;
166		};
167	};
168
169	usart1_hw_ctrl_flow: usart1_hw_ctrl_flow {
170		group1 {
171			pinmux = <PA21A_USART1_RXD>,
172				 <PA24A_USART1_RTS>;
173			bias-pull-up;
174		};
175		group2 {
176			pinmux = <PB4D_USART1_TXD>,
177				 <PA25A_USART1_CTS>;
178		};
179	};
180
181	usart2_default: usart2_default {
182		group1 {
183			pinmux = <PD15B_USART2_RXD>,
184				 <PD16B_USART2_TXD>;
185		};
186	};
187
188	usart2_hw_ctrl_flow_clk: usart2_hw_ctrl_flow_clk {
189		group1 {
190			pinmux = <PD15B_USART2_RXD>,
191				 <PD18B_USART2_RTS>;
192			bias-pull-up;
193		};
194		group2 {
195			pinmux = <PD16B_USART2_TXD>,
196				 <PD19B_USART2_CTS>,
197				 <PD17B_USART2_SCK>;
198		};
199	};
200};
201