1 /*
2  * Copyright (c) 2020 IoT.bzh <julien.massot@iot.bzh>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/arch/cpu.h>
8 #include <zephyr/init.h>
9 #include <soc.h>
10 #include <zephyr/drivers/timer/system_timer.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
13 #include <zephyr/irq.h>
14 
15 #define DT_DRV_COMPAT renesas_rcar_cmt
16 
17 #define TIMER_IRQ              DT_INST_IRQN(0)
18 #define TIMER_BASE_ADDR        DT_INST_REG_ADDR(0)
19 #define TIMER_CLOCK_FREQUENCY  DT_INST_PROP(0, clock_frequency)
20 
21 #define CLOCK_SUBSYS           DT_INST_CLOCKS_CELL(0, module)
22 
23 #define CYCLES_PER_SEC         TIMER_CLOCK_FREQUENCY
24 #define CYCLES_PER_TICK        (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
25 
26 #if defined(CONFIG_TEST)
27 const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_INST(0, renesas_rcar_cmt));
28 #endif
29 static struct rcar_cpg_clk mod_clk = {
30 	.module = DT_INST_CLOCKS_CELL(0, module),
31 	.domain = DT_INST_CLOCKS_CELL(0, domain),
32 };
33 
34 BUILD_ASSERT(CYCLES_PER_TICK > 1,
35 	     "CYCLES_PER_TICK must be greater than 1");
36 
37 #define CMCOR0_OFFSET                   0x018   /* constant register 0 */
38 #define CMCNT0_OFFSET                   0x014   /* counter 0 */
39 #define CMCSR0_OFFSET                   0x010   /* control/status register 0 */
40 
41 #define CMCOR1_OFFSET                   0x118   /* constant register 1 */
42 #define CMCNT1_OFFSET                   0x114   /* counter 1 */
43 #define CMCSR1_OFFSET                   0x110   /* control/status register 1 */
44 
45 #define CMCLKE                          0xB00   /* CLK enable register */
46 #define CLKEN0                          BIT(5)  /* Enable Clock for channel 0 */
47 #define CLKEN1                          BIT(6)  /* Enable Clock for channel 1 */
48 
49 #define CMSTR0_OFFSET                   0x000   /* Timer start register 0 */
50 #define CMSTR1_OFFSET                   0x100   /* Timer start register 1 */
51 #define START_BIT                       BIT(0)
52 
53 #define CSR_CLK_DIV_1                   0x00000007
54 #define CSR_ENABLE_COUNTER_IN_DEBUG     BIT(3)
55 #define CSR_ENABLE_INTERRUPT            BIT(5)
56 #define CSR_FREE_RUN                    BIT(8)
57 #define CSR_WRITE_FLAG                  BIT(13)
58 #define CSR_OVERFLOW_FLAG               BIT(14)
59 #define CSR_MATCH_FLAG                  BIT(15)
60 
cmt_isr(void * arg)61 static void cmt_isr(void *arg)
62 {
63 	ARG_UNUSED(arg);
64 	uint32_t reg_val;
65 
66 	/* clear the interrupt */
67 	reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET);
68 	reg_val &= ~CSR_MATCH_FLAG;
69 	sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET);
70 
71 	/* Announce to the kernel */
72 	sys_clock_announce(1);
73 }
74 
sys_clock_elapsed(void)75 uint32_t sys_clock_elapsed(void)
76 {
77 	/* Always return 0 for tickful operation */
78 	return 0;
79 }
80 
sys_clock_cycle_get_32(void)81 uint32_t sys_clock_cycle_get_32(void)
82 {
83 	return sys_read32(TIMER_BASE_ADDR + CMCNT1_OFFSET);
84 }
85 
86 /*
87  * Initialize both channels at same frequency,
88  * Set the first one to generates interrupt at CYCLES_PER_TICK.
89  * The second one is used for cycles count, the match value is set
90  * at max uint32_t.
91  */
sys_clock_driver_init(void)92 static int sys_clock_driver_init(void)
93 {
94 	const struct device *clk;
95 	uint32_t reg_val;
96 	int i, ret;
97 
98 	clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
99 	if (!device_is_ready(clk)) {
100 		return -ENODEV;
101 	}
102 
103 	ret = clock_control_on(clk, (clock_control_subsys_t)&mod_clk);
104 	if (ret < 0) {
105 		return ret;
106 	}
107 
108 	/* Supply clock for both channels */
109 	sys_write32(CLKEN0 | CLKEN1, TIMER_BASE_ADDR + CMCLKE);
110 
111 	/* Stop both channels */
112 	reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET);
113 	reg_val &= ~START_BIT;
114 	sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET);
115 
116 	reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET);
117 	reg_val &= ~START_BIT;
118 	sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR1_OFFSET);
119 
120 	/* Set the timers as 32-bit, with RCLK/1 clock */
121 	sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1 | CSR_ENABLE_INTERRUPT,
122 		    TIMER_BASE_ADDR + CMCSR0_OFFSET);
123 
124 	/* Do not enable interrupts for the second channel */
125 	sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1,
126 		    TIMER_BASE_ADDR + CMCSR1_OFFSET);
127 
128 	/* Set the first channel match to CYCLES Per tick*/
129 	sys_write32(CYCLES_PER_TICK, TIMER_BASE_ADDR + CMCOR0_OFFSET);
130 
131 	/* Set the second channel match to max uint32 */
132 	sys_write32(0xffffffff, TIMER_BASE_ADDR + CMCOR1_OFFSET);
133 
134 	/* Reset the counter for first channel, check WRFLG first */
135 	while (sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET) & CSR_WRITE_FLAG) {
136 		;
137 	}
138 	sys_write32(0, TIMER_BASE_ADDR + CMCNT0_OFFSET);
139 
140 	for (i = 0; i < 1000; i++) {
141 		if (!sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET)) {
142 			break;
143 		}
144 	}
145 
146 	__ASSERT(sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET) == 0,
147 			"Fail to clear CMCNT0 register");
148 
149 	/* Connect timer interrupt for channel 0*/
150 	IRQ_CONNECT(TIMER_IRQ, 0, cmt_isr, 0, 0);
151 	irq_enable(TIMER_IRQ);
152 
153 	/* Start the timers */
154 	sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR0_OFFSET);
155 	sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR1_OFFSET);
156 
157 	return 0;
158 }
159 
160 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
161 	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
162