1 /*
2 * Copyright (c) 2019 Nordic Semiconductor ASA
3 * Copyright (c) 2019 Ioannis Glaropoulos
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /* Use the NRF_RTC instance for coarse radio event scheduling */
9 #define NRF_RTC NRF_RTC0
10
11 /* Override EVENT_TIMER_ID from 4 to 0, as nRF5340 does not have 4 timer
12 * instances.
13 */
14 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
15 #undef EVENT_TIMER_ID
16 #define EVENT_TIMER_ID 0
17
18 #undef EVENT_TIMER
19 #define EVENT_TIMER _CONCAT(NRF_TIMER, EVENT_TIMER_ID)
20
21 #undef SW_SWITCH_TIMER
22 #define SW_SWITCH_TIMER EVENT_TIMER
23 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
24
25 /* HAL abstraction of event timer prescaler value */
26 #define HAL_EVENT_TIMER_PRESCALER_VALUE 4U
27
28 /* NRF Radio HW timing constants
29 * - provided in US and NS (for higher granularity)
30 * - based on empirical measurements and sniffer logs
31 */
32
33 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
34 * in microseconds for LE 1M PHY.
35 */
36 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_FAST_NS 40900 /*40.1 + 0.8*/
37 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_FAST_US \
38 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_FAST_NS)
39
40 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
41 * in microseconds for LE 1M PHY.
42 */
43 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NS 140900 /*140.1 + 0.8*/
44 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_US \
45 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NS)
46
47 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode
48 * and no HW TIFS auto-switch) in microseconds for LE 1M PHY.
49 */
50 /* 129.5 + 0.8 */
51 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS 130300
52 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US \
53 HAL_RADIO_NS2US_ROUND( \
54 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS)
55
56 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
57 * in microseconds for LE 2M PHY.
58 */
59 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_NS 40000 /* 40.1 - 0.1 */
60 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_US \
61 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_NS)
62
63 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
64 * in microseconds for LE 2M PHY.
65 */
66 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NS 144900 /* 145 - 0.1 */
67 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_US \
68 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NS)
69
70 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and
71 * no HW TIFS auto-switch) in microseconds for LE 2M PHY.
72 */
73 /* 129.5 - 0.1 */
74 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS 129400
75 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US \
76 HAL_RADIO_NS2US_ROUND( \
77 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS)
78
79 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
80 * in microseconds for LE CODED PHY [S2].
81 */
82 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS 42300 /* 40.1 + 2.2 */
83 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_US \
84 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS)
85
86 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
87 * in microseconds for LE 2M PHY [S2].
88 */
89 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132200 /* 130 + 2.2 */
90 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_US \
91 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS)
92
93 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and
94 * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S2].
95 */
96 /* 129.5 + 2.2 */
97 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 131700
98 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US \
99 HAL_RADIO_NS2US_ROUND( \
100 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS)
101
102 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
103 * in microseconds for LE CODED PHY [S8].
104 */
105 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS 42300 /* 40.1 + 2.2 */
106 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_US \
107 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS)
108 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
109 * in microseconds for LE 2M PHY [S8].
110 */
111 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS 121800 /*119.6 + 2.2*/
112 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_US \
113 HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS)
114
115 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and
116 * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S8].
117 */
118 /* 129.5 + 2.2 */
119 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 131700
120 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US \
121 HAL_RADIO_NS2US_ROUND( \
122 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS)
123
124 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
125 * in microseconds for LE 1M PHY.
126 */
127 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_NS 40300 /* 40.1 + 0.2 */
128 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_US \
129 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_NS)
130
131 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
132 * in microseconds for LE 1M PHY.
133 */
134 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NS 140300 /*140.1 + 0.2*/
135 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_US \
136 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NS)
137
138 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and
139 * no HW TIFS auto-switch) in microseconds for LE 1M PHY.
140 */
141 /* 129.5 + 0.2 */
142 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS 129700
143 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US \
144 HAL_RADIO_NS2US_CEIL( \
145 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS)
146
147 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
148 * in microseconds for LE 2M PHY.
149 */
150 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_NS 40300 /* 40.1 + 0.2 */
151 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_US \
152 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_NS)
153
154 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
155 * in microseconds for LE 2M PHY.
156 */
157 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NS 144800 /*144.6 + 0.2*/
158 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_US \
159 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NS)
160
161 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and
162 * no HW TIFS auto-switch) in microseconds for LE 2M PHY.
163 */
164 /* 129.5 + 0.2 */
165 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS 129700
166 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US \
167 HAL_RADIO_NS2US_CEIL( \
168 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS)
169
170 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
171 * in microseconds for LE Coded PHY [S2].
172 */
173 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS 40300 /* 40.1 + 0.2 */
174 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_US \
175 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS)
176
177 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
178 * in microseconds for LE Coded PHY [S2].
179 */
180 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS 130200 /* 130 + 0.2 */
181 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_US \
182 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS)
183
184 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode
185 * and no HW TIFS auto-switch) in microseconds for LE Coded PHY [S2].
186 */
187 /* 129.5 + 0.2 */
188 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 129700
189 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US \
190 HAL_RADIO_NS2US_CEIL( \
191 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS)
192
193 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
194 * in microseconds for LE Coded PHY [S8].
195 */
196 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS 40300 /* 40.1 + 0.2 */
197 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_US \
198 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS)
199
200 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
201 * in microseconds for LE Coded PHY [S8].
202 */
203 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120200 /* 120.0 + 0.2 */
204 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_US \
205 HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS)
206
207 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and
208 * no HW TIFS auto-switch) in microseconds for LE Coded PHY [S8].
209 */
210 /* 129.5 + 0.2 */
211 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 129700
212 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US \
213 HAL_RADIO_NS2US_CEIL( \
214 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS)
215
216 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_1M_US 1 /* ceil(0.6) */
217 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_1M_NS 600 /* 0.6 */
218 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_2M_US 1 /* ceil(0.6) */
219 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_2M_NS 600 /* 0.6 */
220 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S2_US 1 /* ceil(0.6) */
221 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S2_NS 600 /* 0.6 */
222 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S8_US 1 /* ceil(0.6) */
223 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S8_NS 600 /* 0.6 */
224
225 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_US 10 /* ceil(9.4) */
226 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_NS 9400 /* 9.4 */
227 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_US 5 /* ceil(5.0) */
228 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_NS 5000 /* 5.0 */
229 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_US 25 /* ceil(19.6) */
230 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_NS 24600 /* 19.6 */
231 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_US 30 /* ceil(29.6) */
232 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_NS 29600 /* 29.6 */
233
234 #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST)
235 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \
236 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_FAST_US
237 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_NS \
238 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_FAST_NS
239
240 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_US \
241 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_US
242 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \
243 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_NS
244
245 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \
246 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_US
247 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \
248 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS
249
250 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \
251 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_US
252 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \
253 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS
254
255 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \
256 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_US
257 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \
258 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_NS
259
260 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_US \
261 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_US
262 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \
263 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_NS
264
265 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \
266 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_US
267 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \
268 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS
269
270 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \
271 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_US
272 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \
273 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS
274
275 #else /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
276 #if defined(CONFIG_BT_CTLR_TIFS_HW)
277 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \
278 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_US
279 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_NS \
280 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NS
281
282 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_US \
283 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_US
284 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \
285 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NS
286
287 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \
288 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_US
289 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \
290 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS
291
292 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \
293 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_US
294 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \
295 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS
296
297 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \
298 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_US
299 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \
300 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NS
301
302 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_US \
303 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_US
304 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \
305 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NS
306
307 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \
308 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_US
309 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \
310 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS
311
312 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \
313 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_US
314 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \
315 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS
316
317 #else /* !CONFIG_BT_CTLR_TIFS_HW */
318 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \
319 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US
320 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_NS \
321 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS
322
323 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_US \
324 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US
325 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \
326 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS
327
328 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \
329 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US
330 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \
331 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS
332
333 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \
334 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US
335 #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \
336 HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS
337
338 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \
339 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US
340 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \
341 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS
342
343 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_US \
344 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US
345 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \
346 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS
347
348 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \
349 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US
350 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \
351 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS
352
353 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \
354 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US
355 #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \
356 HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS
357 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
358 #endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
359
360 /* nRF5340 supports +3dBm Tx Power using high voltage request, define +3dBm
361 * value for Controller use.
362 */
363 #ifndef RADIO_TXPOWER_TXPOWER_Pos3dBm
364 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL)
365 #endif
366
367 /* HAL abstraction of Radio bitfields */
368 #define HAL_NRF_RADIO_EVENT_END NRF_RADIO_EVENT_END
369 #define HAL_RADIO_EVENTS_END EVENTS_END
370 #define HAL_RADIO_PUBLISH_END PUBLISH_END
371 #define HAL_NRF_RADIO_EVENT_PHYEND NRF_RADIO_EVENT_PHYEND
372 #define HAL_RADIO_EVENTS_PHYEND EVENTS_PHYEND
373 #define HAL_RADIO_PUBLISH_PHYEND PUBLISH_PHYEND
374 #define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
375 #define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
376 #define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
377 #define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear RADIO_CLEARPATTERN_CLEARPATTERN_Clear
378
379 /* HAL abstraction of Radio IRQ number */
380 #define HAL_RADIO_IRQn RADIO_IRQn
381
382 /* SoC specific NRF_RADIO power-on reset value. Refer to Product Specification,
383 * RADIO Registers section for the documented reset values.
384 *
385 * NOTE: Only implementation used values defined here.
386 * In the future if MDK or nRFx header include these, use them instead.
387 */
388 #define HAL_RADIO_RESET_VALUE_DFEMODE 0x00000000UL
389 #define HAL_RADIO_RESET_VALUE_CTEINLINECONF 0x00002800UL
390
391 static inline void hal_radio_tx_power_high_voltage_clear(void);
392
hal_radio_reset(void)393 static inline void hal_radio_reset(void)
394 {
395 /* TODO: Add any required setup for each radio event
396 */
397 }
398
hal_radio_stop(void)399 static inline void hal_radio_stop(void)
400 {
401 /* If +3dBm Tx power was used, then turn off high voltage when radio not
402 * used.
403 */
404 hal_radio_tx_power_high_voltage_clear();
405
406 /* TODO: Add any required cleanup of actions taken in hal_radio_reset()
407 */
408 }
409
hal_radio_ram_prio_setup(void)410 static inline void hal_radio_ram_prio_setup(void)
411 {
412 /* TODO */
413 }
414
hal_radio_phy_mode_get(uint8_t phy,uint8_t flags)415 static inline uint32_t hal_radio_phy_mode_get(uint8_t phy, uint8_t flags)
416 {
417 uint32_t mode;
418
419 switch (phy) {
420 case BIT(0):
421 default:
422 mode = RADIO_MODE_MODE_Ble_1Mbit;
423
424 /* Workaround: nRF5340 Revision 1 Errata 117 */
425 *((volatile uint32_t *)0x41008588) =
426 *((volatile uint32_t *)0x01FF0080); /* non-2M mode */
427 break;
428
429 case BIT(1):
430 mode = RADIO_MODE_MODE_Ble_2Mbit;
431
432 /* Workaround: nRF5340 Revision 1 Errata 117 */
433 *((volatile uint32_t *)0x41008588) =
434 *((volatile uint32_t *)0x01FF0084); /* 2M mode */
435 break;
436
437 #if defined(CONFIG_BT_CTLR_PHY_CODED)
438 case BIT(2):
439 if (flags & 0x01) {
440 mode = RADIO_MODE_MODE_Ble_LR125Kbit;
441 } else {
442 mode = RADIO_MODE_MODE_Ble_LR500Kbit;
443 }
444
445 /* Workaround: nRF5340 Revision 1 Errata 117 */
446 *((volatile uint32_t *)0x41008588) =
447 *((volatile uint32_t *)0x01FF0080); /* non-2M mode */
448 break;
449 #endif /* CONFIG_BT_CTLR_PHY_CODED */
450 }
451
452 return mode;
453 }
454
hal_radio_tx_power_max_get(void)455 static inline uint32_t hal_radio_tx_power_max_get(void)
456 {
457 return RADIO_TXPOWER_TXPOWER_0dBm;
458 }
459
hal_radio_tx_power_min_get(void)460 static inline uint32_t hal_radio_tx_power_min_get(void)
461 {
462 return RADIO_TXPOWER_TXPOWER_Neg40dBm;
463 }
464
hal_radio_tx_power_floor(int8_t tx_power_lvl)465 static inline uint32_t hal_radio_tx_power_floor(int8_t tx_power_lvl)
466 {
467 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_0dBm) {
468 return RADIO_TXPOWER_TXPOWER_0dBm;
469 }
470
471 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg1dBm) {
472 return RADIO_TXPOWER_TXPOWER_Neg1dBm;
473 }
474
475 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg2dBm) {
476 return RADIO_TXPOWER_TXPOWER_Neg2dBm;
477 }
478
479 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg3dBm) {
480 return RADIO_TXPOWER_TXPOWER_Neg3dBm;
481 }
482
483 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg4dBm) {
484 return RADIO_TXPOWER_TXPOWER_Neg4dBm;
485 }
486
487 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg5dBm) {
488 return RADIO_TXPOWER_TXPOWER_Neg5dBm;
489 }
490
491 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg6dBm) {
492 return RADIO_TXPOWER_TXPOWER_Neg6dBm;
493 }
494
495 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg7dBm) {
496 return RADIO_TXPOWER_TXPOWER_Neg7dBm;
497 }
498
499 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg8dBm) {
500 return RADIO_TXPOWER_TXPOWER_Neg8dBm;
501 }
502
503 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg12dBm) {
504 return RADIO_TXPOWER_TXPOWER_Neg12dBm;
505 }
506
507 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg16dBm) {
508 return RADIO_TXPOWER_TXPOWER_Neg16dBm;
509 }
510
511 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Neg20dBm) {
512 return RADIO_TXPOWER_TXPOWER_Neg20dBm;
513 }
514
515 /* Note: The -30 dBm power level is deprecated so ignore it! */
516 return RADIO_TXPOWER_TXPOWER_Neg40dBm;
517 }
518
hal_radio_tx_power_high_voltage_set(int8_t tx_power_lvl)519 static inline void hal_radio_tx_power_high_voltage_set(int8_t tx_power_lvl)
520 {
521 if (tx_power_lvl >= (int8_t)RADIO_TXPOWER_TXPOWER_Pos3dBm) {
522 nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL, true);
523 }
524 }
525
hal_radio_tx_power_high_voltage_clear(void)526 static inline void hal_radio_tx_power_high_voltage_clear(void)
527 {
528 nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL, false);
529 }
530
hal_radio_tx_ready_delay_us_get(uint8_t phy,uint8_t flags)531 static inline uint32_t hal_radio_tx_ready_delay_us_get(uint8_t phy, uint8_t flags)
532 {
533 switch (phy) {
534 default:
535 case BIT(0):
536 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US;
537 case BIT(1):
538 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_US;
539
540 #if defined(CONFIG_BT_CTLR_PHY_CODED)
541 case BIT(2):
542 if (flags & 0x01) {
543 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US;
544 } else {
545 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US;
546 }
547 #endif /* CONFIG_BT_CTLR_PHY_CODED */
548 }
549 }
550
hal_radio_rx_ready_delay_us_get(uint8_t phy,uint8_t flags)551 static inline uint32_t hal_radio_rx_ready_delay_us_get(uint8_t phy, uint8_t flags)
552 {
553 switch (phy) {
554 default:
555 case BIT(0):
556 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US;
557 case BIT(1):
558 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_US;
559
560 #if defined(CONFIG_BT_CTLR_PHY_CODED)
561 case BIT(2):
562 if (flags & 0x01) {
563 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US;
564 } else {
565 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US;
566 }
567 #endif /* CONFIG_BT_CTLR_PHY_CODED */
568 }
569 }
570
hal_radio_tx_chain_delay_us_get(uint8_t phy,uint8_t flags)571 static inline uint32_t hal_radio_tx_chain_delay_us_get(uint8_t phy, uint8_t flags)
572 {
573 switch (phy) {
574 default:
575 case BIT(0):
576 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_1M_US;
577 case BIT(1):
578 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_2M_US;
579
580 #if defined(CONFIG_BT_CTLR_PHY_CODED)
581 case BIT(2):
582 if (flags & 0x01) {
583 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S8_US;
584 } else {
585 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S2_US;
586 }
587 #endif /* CONFIG_BT_CTLR_PHY_CODED */
588 }
589 }
590
hal_radio_rx_chain_delay_us_get(uint8_t phy,uint8_t flags)591 static inline uint32_t hal_radio_rx_chain_delay_us_get(uint8_t phy, uint8_t flags)
592 {
593 switch (phy) {
594 default:
595 case BIT(0):
596 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_US;
597 case BIT(1):
598 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_US;
599
600 #if defined(CONFIG_BT_CTLR_PHY_CODED)
601 case BIT(2):
602 if (flags & 0x01) {
603 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_US;
604 } else {
605 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_US;
606 }
607 #endif /* CONFIG_BT_CTLR_PHY_CODED */
608 }
609 }
610
hal_radio_tx_ready_delay_ns_get(uint8_t phy,uint8_t flags)611 static inline uint32_t hal_radio_tx_ready_delay_ns_get(uint8_t phy, uint8_t flags)
612 {
613 switch (phy) {
614 default:
615 case BIT(0):
616 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_NS;
617 case BIT(1):
618 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS;
619
620 #if defined(CONFIG_BT_CTLR_PHY_CODED)
621 case BIT(2):
622 if (flags & 0x01) {
623 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS;
624 } else {
625 return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS;
626 }
627 #endif /* CONFIG_BT_CTLR_PHY_CODED */
628 }
629 }
630
hal_radio_rx_ready_delay_ns_get(uint8_t phy,uint8_t flags)631 static inline uint32_t hal_radio_rx_ready_delay_ns_get(uint8_t phy, uint8_t flags)
632 {
633 switch (phy) {
634 default:
635 case BIT(0):
636 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS;
637 case BIT(1):
638 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS;
639
640 #if defined(CONFIG_BT_CTLR_PHY_CODED)
641 case BIT(2):
642 if (flags & 0x01) {
643 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS;
644 } else {
645 return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS;
646 }
647 #endif /* CONFIG_BT_CTLR_PHY_CODED */
648 }
649 }
650
hal_radio_tx_chain_delay_ns_get(uint8_t phy,uint8_t flags)651 static inline uint32_t hal_radio_tx_chain_delay_ns_get(uint8_t phy, uint8_t flags)
652 {
653 switch (phy) {
654 default:
655 case BIT(0):
656 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_1M_NS;
657 case BIT(1):
658 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_2M_NS;
659
660 #if defined(CONFIG_BT_CTLR_PHY_CODED)
661 case BIT(2):
662 if (flags & 0x01) {
663 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S8_NS;
664 } else {
665 return HAL_RADIO_NRF5340_TX_CHAIN_DELAY_S2_NS;
666 }
667 #endif /* CONFIG_BT_CTLR_PHY_CODED */
668 }
669 }
670
hal_radio_rx_chain_delay_ns_get(uint8_t phy,uint8_t flags)671 static inline uint32_t hal_radio_rx_chain_delay_ns_get(uint8_t phy, uint8_t flags)
672 {
673 switch (phy) {
674 default:
675 case BIT(0):
676 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_NS;
677 case BIT(1):
678 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_NS;
679
680 #if defined(CONFIG_BT_CTLR_PHY_CODED)
681 case BIT(2):
682 if (flags & 0x01) {
683 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_NS;
684 } else {
685 return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_NS;
686 }
687 #endif /* CONFIG_BT_CTLR_PHY_CODED */
688 }
689 }
690
