1/*
2 * Copyright (c) 2020, Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <mem.h>
10#include "skeleton.dtsi"
11
12#define DT_FLASH_SIZE		DT_SIZE_M(4)
13#define DT_SRAM_SIZE		DT_SIZE_M(4)
14
15/ {
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19	};
20
21	intc: arcv2-intc {
22		compatible = "snps,arcv2-intc";
23		interrupt-controller;
24		#interrupt-cells = <2>;
25	};
26
27	timer0: timer0 {
28		compatible = "snps,arc-timer";
29		interrupts = <16 1>;
30		interrupt-parent = <&intc>;
31	};
32
33	timer1: timer1 {
34		compatible = "snps,arc-timer";
35		interrupts = <17 1>;
36		interrupt-parent = <&intc>;
37	};
38
39	/* We are carving out of DRAM for a pseudo flash and sram region */
40	flash0: flash@80000000 {
41		compatible = "soc-nv-flash";
42		reg = <0x80000000 DT_FLASH_SIZE>;
43	};
44
45	sram0: sram@80400000 {
46		device_type = "memory";
47		reg = <0x80400000 DT_SRAM_SIZE>;
48	};
49
50	ns16550_uart0: uart@f0000000 {
51		compatible = "ns16550";
52		clock-frequency = <10000000>;
53		reg = <0xf0000000 0x400>;
54		current-speed = <115200>;
55		interrupt-parent = <&intc>;
56		interrupts = <24 1>;
57		reg-shift = <2>;
58	};
59
60	ns16550_uart1: uart@f0002000 {
61		compatible = "ns16550";
62		clock-frequency = <10000000>;
63		reg = <0xf0002000 0x400>;
64		current-speed = <115200>;
65		interrupt-parent = <&intc>;
66		interrupts = <25 1>;
67		reg-shift = <2>;
68	};
69
70	chosen {
71		zephyr,sram = &sram0;
72		zephyr,flash = &flash0;
73		zephyr,console = &ns16550_uart0;
74		zephyr,shell-uart = &ns16550_uart0;
75		zephyr,uart-pipe = &ns16550_uart1;
76	};
77};
78