1 /**************************************************************************//** 2 * @file qei_reg.h 3 * @version V1.00 4 * @brief QEI register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __QEI_REG_H__ 10 #define __QEI_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Quadrature Encoder Interface -------------------------*/ 19 /** 20 @addtogroup QEI Quadrature Encoder Interface(QEI) 21 Memory Mapped Structure for QEI Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var QEI_T::CNT 31 * Offset: 0x00 QEI Counter Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[31:0] |CNT |Quadrature Encoder Interface Counter 36 * | | |A 32-bit up/down counter 37 * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero 38 * | | |This register performs an integrator which count value is proportional to the encoder position 39 * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: 40 * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. 41 * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode. 42 * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1. 43 * @var QEI_T::CNTHOLD 44 * Offset: 0x04 QEI Counter Hold Register 45 * --------------------------------------------------------------------------------------------------- 46 * |Bits |Field |Descriptions 47 * | :----: | :----: | :---- | 48 * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold 49 * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. 50 * @var QEI_T::CNTLATCH 51 * Offset: 0x08 QEI Counter Index Latch Register 52 * --------------------------------------------------------------------------------------------------- 53 * |Bits |Field |Descriptions 54 * | :----: | :----: | :---- | 55 * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch 56 * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. 57 * @var QEI_T::CNTCMP 58 * Offset: 0x0C QEI Counter Compare Register 59 * --------------------------------------------------------------------------------------------------- 60 * |Bits |Field |Descriptions 61 * | :----: | :----: | :---- | 62 * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare 63 * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set 64 * | | |This register is software writable. 65 * @var QEI_T::CNTMAX 66 * Offset: 0x14 QEI Pre-set Maximum Count Register 67 * --------------------------------------------------------------------------------------------------- 68 * |Bits |Field |Descriptions 69 * | :----: | :----: | :---- | 70 * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count 71 * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode 72 * @var QEI_T::CTL 73 * Offset: 0x18 QEI Controller Control Register 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection 78 * | | |To determine the sampling frequency of the Noise Filter clock . 79 * | | |000 = QEI_CLK. 80 * | | |001 = QEI_CLK/2. 81 * | | |010 = QEI_CLK/4. 82 * | | |011 = QEI_CLK/16. 83 * | | |100 = QEI_CLK/32. 84 * | | |101 = QEI_CLK/64. 85 * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit 86 * | | |0 = The noise filter of QEI controller Enabled. 87 * | | |1 = The noise filter of QEI controller Disabled. 88 * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit 89 * | | |0 = QEA input to QEI Controller Disabled. 90 * | | |1 = QEA input to QEI Controller Enabled. 91 * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit 92 * | | |0 = QEB input to QEI Controller Disabled. 93 * | | |1 = QEB input to QEI Controller Enabled. 94 * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit 95 * | | |0 = IDX input to QEI Controller Disabled. 96 * | | |1 = IDX input to QEI Controller Enabled. 97 * |[9:8] |MODE |QEI Counting Mode Selection 98 * | | |There are four quadrature encoder pulse counter operation modes. 99 * | | |00 = X4 Free-counting Mode. 100 * | | |01 = X2 Free-counting Mode. 101 * | | |10 = X4 Compare-counting Mode. 102 * | | |11 = X2 Compare-counting Mode. 103 * |[12] |CHAINV |Inverse QEA Input Polarity 104 * | | |0 = Not inverse QEA input polarity. 105 * | | |1 = QEA input polarity is inverse to QEI controller. 106 * |[13] |CHBINV |Inverse QEB Input Polarity 107 * | | |0 = Not inverse QEB input polarity. 108 * | | |1 = QEB input polarity is inverse to QEI controller. 109 * |[14] |IDXINV |Inverse IDX Input Polarity 110 * | | |0 = Not inverse IDX input polarity. 111 * | | |1 = IDX input polarity is inverse to QEI controller. 112 * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit 113 * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. 114 * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. 115 * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit 116 * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. 117 * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. 118 * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit 119 * | | |0 = CMPF can trigger QEI controller interrupt Disabled. 120 * | | |1 = CMPF can trigger QEI controller interrupt Enabled. 121 * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit 122 * | | |0 = The IDXF can trigger QEI interrupt Disabled. 123 * | | |1 = The IDXF can trigger QEI interrupt Enabled. 124 * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 125 * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. 126 * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. 127 * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 128 * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. 129 * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. 130 * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 131 * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. 132 * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. 133 * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 134 * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. 135 * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. 136 * |[24] |HOLDCNT |Hold QEI_CNT Control 137 * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD 138 * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). 139 * | | |0 = No operation. 140 * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD. 141 * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. 142 * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit 143 * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX. 144 * | | |0 = The index signal latch QEI counter function Disabled. 145 * | | |1 = The index signal latch QEI counter function Enabled. 146 * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit 147 * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0). 148 * | | |0 = Reload function Disabled. 149 * | | |1 = QEI_CNT re-initialized by Index signal Enabled. 150 * |[28] |CMPEN |the Compare Function Enable Bit 151 * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. 152 * | | |0 = Compare function Disabled. 153 * | | |1 = Compare function Enabled. 154 * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit 155 * | | |0 = QEI controller function Disabled. 156 * | | |1 = QEI controller function Enabled. 157 * @var QEI_T::STATUS 158 * Offset: 0x2C QEI Controller Status Register 159 * --------------------------------------------------------------------------------------------------- 160 * |Bits |Field |Descriptions 161 * | :----: | :----: | :---- | 162 * |[0] |IDXF |IDX Detected Flag 163 * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. 164 * | | |0 = No rising edge detected on signal CHX. 165 * | | |1 = A rising edge occurs on signal CHX. 166 * | | |Note: This bit is only cleared by writing 1 to it. 167 * |[1] |CMPF |Compare-match Flag 168 * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). 169 * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). 170 * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). 171 * | | |Note: This bit is only cleared by writing 1 to it. 172 * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag 173 * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode 174 * | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). 175 * | | |0 = No overflow or underflow occurs in QEI counter. 176 * | | |1 = QEI counter occurs counting overflow or underflow. 177 * | | |Note: This bit is only cleared by writing 1 to it. 178 * |[3] |DIRCHGF |Direction Change Flag 179 * | | |Flag is set by hardware while QEI counter counting direction is changed 180 * | | |Software can clear this bit by writing 1 to it. 181 * | | |0 = No change in QEI counter counting direction. 182 * | | |1 = QEI counter counting direction is changed. 183 * | | |Note: This bit is only cleared by writing 1 to it. 184 * |[8] |DIRF |QEI Counter Counting Direction Indication 185 * | | |0 = QEI Counter is in down-counting. 186 * | | |1 = QEI Counter is in up-counting. 187 * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. 188 */ 189 __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ 190 __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ 191 __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ 192 __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ 193 __I uint32_t RESERVE0[1]; 194 __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ 195 __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ 196 __I uint32_t RESERVE1[4]; 197 __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ 198 199 } QEI_T; 200 201 /** 202 @addtogroup QEI_CONST QEI Bit Field Definition 203 Constant Definitions for QEI Controller 204 @{ 205 */ 206 207 #define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ 208 #define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ 209 210 #define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ 211 #define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ 212 213 #define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ 214 #define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ 215 216 #define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ 217 #define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ 218 219 #define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ 220 #define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ 221 222 #define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ 223 #define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ 224 225 #define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ 226 #define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ 227 228 #define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ 229 #define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ 230 231 #define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ 232 #define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ 233 234 #define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ 235 #define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ 236 237 #define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ 238 #define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ 239 240 #define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ 241 #define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ 242 243 #define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ 244 #define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ 245 246 #define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ 247 #define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ 248 249 #define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ 250 #define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ 251 252 #define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ 253 #define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ 254 255 #define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ 256 #define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ 257 258 #define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ 259 #define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ 260 261 #define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ 262 #define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ 263 264 #define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ 265 #define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ 266 267 #define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ 268 #define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ 269 270 #define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ 271 #define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ 272 273 #define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ 274 #define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ 275 276 #define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ 277 #define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ 278 279 #define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ 280 #define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ 281 282 #define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ 283 #define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ 284 285 #define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ 286 #define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ 287 288 #define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ 289 #define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ 290 291 #define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ 292 #define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ 293 294 #define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ 295 #define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ 296 297 #define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ 298 #define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ 299 300 #define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ 301 #define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ 302 303 /**@}*/ /* QEI_CONST */ 304 /**@}*/ /* end of QEI register group */ 305 /**@}*/ /* end of REGISTER group */ 306 307 308 #endif /* __QEI_REG_H__ */ 309
