1 /*
2 * Copyright (c) 2018, Cue Health Inc
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <nrfx_pwm.h>
7 #include <zephyr/drivers/pwm.h>
8 #include <zephyr/pm/device.h>
9 #include <zephyr/drivers/pinctrl.h>
10 #include <soc.h>
11 #include <hal/nrf_gpio.h>
12 #include <stdbool.h>
13
14 #include <zephyr/logging/log.h>
15
16 LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
17
18 /* NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED can be undefined or defined
19 * to 0 or 1, hence the use of #if IS_ENABLED().
20 */
21 #if IS_ENABLED(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
22 #define ANOMALY_109_IRQ_CONNECT(...) IRQ_CONNECT(__VA_ARGS__)
23 #define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
24 #define _EGU_IRQ_CONNECT(idx) \
25 extern void nrfx_egu_##idx##_irq_handler(void); \
26 IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
27 DT_IRQ(DT_NODELABEL(egu##idx), priority), \
28 nrfx_isr, nrfx_egu_##idx##_irq_handler, 0)
29 #else
30 #define ANOMALY_109_IRQ_CONNECT(...)
31 #define ANOMALY_109_EGU_IRQ_CONNECT(idx)
32 #endif
33
34 #define PWM_NRFX_CH_POLARITY_MASK BIT(15)
35 #define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
36 #define PWM_NRFX_CH_VALUE(compare_value, inverted) \
37 (compare_value | (inverted ? 0 : PWM_NRFX_CH_POLARITY_MASK))
38
39 struct pwm_nrfx_config {
40 nrfx_pwm_t pwm;
41 nrfx_pwm_config_t initial_config;
42 nrf_pwm_sequence_t seq;
43 const struct pinctrl_dev_config *pcfg;
44 };
45
46 struct pwm_nrfx_data {
47 uint32_t period_cycles;
48 uint16_t seq_values[NRF_PWM_CHANNEL_COUNT];
49 /* Bit mask indicating channels that need the PWM generation. */
50 uint8_t pwm_needed;
51 uint8_t prescaler;
52 bool stop_requested;
53 };
54 /* Ensure the pwm_needed bit mask can accommodate all available channels. */
55 #if (NRF_PWM_CHANNEL_COUNT > 8)
56 #error "Current implementation supports maximum 8 channels."
57 #endif
58
59
pwm_period_check_and_set(const struct device * dev,uint32_t channel,uint32_t period_cycles)60 static bool pwm_period_check_and_set(const struct device *dev,
61 uint32_t channel, uint32_t period_cycles)
62 {
63 const struct pwm_nrfx_config *config = dev->config;
64 struct pwm_nrfx_data *data = dev->data;
65 uint8_t prescaler;
66 uint32_t countertop;
67
68 /* If the currently configured period matches the requested one,
69 * nothing more needs to be done.
70 */
71 if (period_cycles == data->period_cycles) {
72 return true;
73 }
74
75 /* If any other channel is driven by the PWM peripheral, the period
76 * that is currently set cannot be changed, as this would influence
77 * the output for that channel.
78 */
79 if ((data->pwm_needed & ~BIT(channel)) != 0) {
80 LOG_ERR("Incompatible period.");
81 return false;
82 }
83
84 /* Try to find a prescaler that will allow setting the requested period
85 * after prescaling as the countertop value for the PWM peripheral.
86 */
87 prescaler = 0;
88 countertop = period_cycles;
89 do {
90 if (countertop <= PWM_COUNTERTOP_COUNTERTOP_Msk) {
91 data->period_cycles = period_cycles;
92 data->prescaler = prescaler;
93
94 nrf_pwm_configure(config->pwm.p_reg,
95 data->prescaler,
96 config->initial_config.count_mode,
97 (uint16_t)countertop);
98 return true;
99 }
100
101 countertop >>= 1;
102 ++prescaler;
103 } while (prescaler <= PWM_PRESCALER_PRESCALER_Msk);
104
105 LOG_ERR("Prescaler for period_cycles %u not found.", period_cycles);
106 return false;
107 }
108
channel_psel_get(uint32_t channel,uint32_t * psel,const struct pwm_nrfx_config * config)109 static bool channel_psel_get(uint32_t channel, uint32_t *psel,
110 const struct pwm_nrfx_config *config)
111 {
112 *psel = nrf_pwm_pin_get(config->pwm.p_reg, (uint8_t)channel);
113
114 return (((*psel & PWM_PSEL_OUT_CONNECT_Msk) >> PWM_PSEL_OUT_CONNECT_Pos)
115 == PWM_PSEL_OUT_CONNECT_Connected);
116 }
117
pwm_nrfx_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)118 static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
119 uint32_t period_cycles, uint32_t pulse_cycles,
120 pwm_flags_t flags)
121 {
122 /* We assume here that period_cycles will always be 16MHz
123 * peripheral clock. Since pwm_nrfx_get_cycles_per_sec() function might
124 * be removed, see ISSUE #6958.
125 * TODO: Remove this comment when issue has been resolved.
126 */
127 const struct pwm_nrfx_config *config = dev->config;
128 struct pwm_nrfx_data *data = dev->data;
129 uint16_t compare_value;
130 bool inverted = (flags & PWM_POLARITY_INVERTED);
131 bool needs_pwm = false;
132
133 if (channel >= NRF_PWM_CHANNEL_COUNT) {
134 LOG_ERR("Invalid channel: %u.", channel);
135 return -EINVAL;
136 }
137
138 /* If this PWM is in center-aligned mode, pulse and period lengths
139 * are effectively doubled by the up-down count, so halve them here
140 * to compensate.
141 */
142 if (config->initial_config.count_mode == NRF_PWM_MODE_UP_AND_DOWN) {
143 period_cycles /= 2;
144 pulse_cycles /= 2;
145 }
146
147 if (pulse_cycles == 0) {
148 /* Constantly inactive (duty 0%). */
149 compare_value = 0;
150 } else if (pulse_cycles >= period_cycles) {
151 /* Constantly active (duty 100%). */
152 /* This value is always greater than or equal to COUNTERTOP. */
153 compare_value = PWM_NRFX_CH_COMPARE_MASK;
154 } else {
155 /* PWM generation needed. Check if the requested period matches
156 * the one that is currently set, or the PWM peripheral can be
157 * reconfigured accordingly.
158 */
159 if (!pwm_period_check_and_set(dev, channel, period_cycles)) {
160 return -EINVAL;
161 }
162
163 compare_value = (uint16_t)(pulse_cycles >> data->prescaler);
164 needs_pwm = true;
165 }
166
167 data->seq_values[channel] = PWM_NRFX_CH_VALUE(compare_value, inverted);
168
169 LOG_DBG("channel %u, pulse %u, period %u, prescaler: %u.",
170 channel, pulse_cycles, period_cycles, data->prescaler);
171
172 /* If this channel does not need to be driven by the PWM peripheral
173 * because its state is to be constant (duty 0% or 100%), set properly
174 * the GPIO configuration for its output pin. This will provide
175 * the correct output state for this channel when the PWM peripheral
176 * is stopped.
177 */
178 if (!needs_pwm) {
179 uint32_t psel;
180
181 if (channel_psel_get(channel, &psel, config)) {
182 uint32_t out_level = (pulse_cycles == 0) ? 0 : 1;
183
184 if (inverted) {
185 out_level ^= 1;
186 }
187
188 nrf_gpio_pin_write(psel, out_level);
189 }
190
191 data->pwm_needed &= ~BIT(channel);
192 } else {
193 data->pwm_needed |= BIT(channel);
194 }
195
196 /* If the PWM generation is not needed for any channel (all are set
197 * to constant inactive or active state), stop the PWM peripheral.
198 * Otherwise, request a playback of the defined sequence so that
199 * the PWM peripheral loads `seq_values` into its internal compare
200 * registers and drives its outputs accordingly.
201 */
202 if (data->pwm_needed == 0) {
203 /* Don't wait here for the peripheral to actually stop. Instead,
204 * ensure it is stopped before starting the next playback.
205 */
206 nrfx_pwm_stop(&config->pwm, false);
207 data->stop_requested = true;
208 } else {
209 if (data->stop_requested) {
210 data->stop_requested = false;
211
212 /* After a stop is requested, the PWM peripheral stops
213 * pulse generation at the end of the current period,
214 * and till that moment, it ignores any start requests,
215 * so ensure here that it is stopped.
216 */
217 while (!nrfx_pwm_stopped_check(&config->pwm)) {
218 }
219 }
220
221 /* It is sufficient to play the sequence once without looping.
222 * The PWM generation will continue with the loaded values
223 * until another playback is requested (new values will be
224 * loaded then) or the PWM peripheral is stopped.
225 */
226 nrfx_pwm_simple_playback(&config->pwm, &config->seq, 1, 0);
227 }
228
229 return 0;
230 }
231
pwm_nrfx_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)232 static int pwm_nrfx_get_cycles_per_sec(const struct device *dev, uint32_t channel,
233 uint64_t *cycles)
234 {
235 /* TODO: Since this function might be removed, we will always return
236 * 16MHz from this function and handle the conversion with prescaler,
237 * etc, in the pin set function. See issue #6958.
238 */
239 *cycles = 16ul * 1000ul * 1000ul;
240
241 return 0;
242 }
243
244 static const struct pwm_driver_api pwm_nrfx_drv_api_funcs = {
245 .set_cycles = pwm_nrfx_set_cycles,
246 .get_cycles_per_sec = pwm_nrfx_get_cycles_per_sec,
247 };
248
pwm_nrfx_init(const struct device * dev)249 static int pwm_nrfx_init(const struct device *dev)
250 {
251 const struct pwm_nrfx_config *config = dev->config;
252 struct pwm_nrfx_data *data = dev->data;
253 uint8_t initially_inverted = 0;
254
255 int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
256
257 ANOMALY_109_EGU_IRQ_CONNECT(NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE);
258
259 if (ret < 0) {
260 return ret;
261 }
262
263 for (size_t i = 0; i < ARRAY_SIZE(data->seq_values); i++) {
264 uint32_t psel;
265
266 if (channel_psel_get(i, &psel, config)) {
267 /* Mark channels as inverted according to what initial
268 * state of their outputs has been set by pinctrl (high
269 * idle state means that the channel is inverted).
270 */
271 initially_inverted |= nrf_gpio_pin_out_read(psel) ?
272 BIT(i) : 0;
273 }
274 }
275
276 for (size_t i = 0; i < ARRAY_SIZE(data->seq_values); i++) {
277 bool inverted = initially_inverted & BIT(i);
278
279 data->seq_values[i] = PWM_NRFX_CH_VALUE(0, inverted);
280 }
281
282 nrfx_err_t result = nrfx_pwm_init(&config->pwm,
283 &config->initial_config,
284 NULL,
285 NULL);
286 if (result != NRFX_SUCCESS) {
287 LOG_ERR("Failed to initialize device: %s", dev->name);
288 return -EBUSY;
289 }
290
291 return 0;
292 }
293
294 #ifdef CONFIG_PM_DEVICE
pwm_nrfx_uninit(const struct device * dev)295 static void pwm_nrfx_uninit(const struct device *dev)
296 {
297 const struct pwm_nrfx_config *config = dev->config;
298
299 nrfx_pwm_uninit(&config->pwm);
300
301 memset(dev->data, 0, sizeof(struct pwm_nrfx_data));
302 }
303
pwm_nrfx_pm_action(const struct device * dev,enum pm_device_action action)304 static int pwm_nrfx_pm_action(const struct device *dev,
305 enum pm_device_action action)
306 {
307 const struct pwm_nrfx_config *config = dev->config;
308 int ret = 0;
309
310 switch (action) {
311 case PM_DEVICE_ACTION_RESUME:
312 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
313 if (ret < 0) {
314 return ret;
315 }
316 ret = pwm_nrfx_init(dev);
317 break;
318
319 case PM_DEVICE_ACTION_SUSPEND:
320 pwm_nrfx_uninit(dev);
321
322 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
323 if (ret < 0) {
324 return ret;
325 }
326 break;
327
328 default:
329 return -ENOTSUP;
330 }
331
332 return ret;
333 }
334 #else
335
336 #define pwm_nrfx_pm_action NULL
337
338 #endif /* CONFIG_PM_DEVICE */
339
340 #define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
341 #define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
342
343 #define PWM_NRFX_DEVICE(idx) \
344 NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(PWM(idx)); \
345 static struct pwm_nrfx_data pwm_nrfx_##idx##_data; \
346 PINCTRL_DT_DEFINE(PWM(idx)); \
347 static const struct pwm_nrfx_config pwm_nrfx_##idx##_config = { \
348 .pwm = NRFX_PWM_INSTANCE(idx), \
349 .initial_config = { \
350 .skip_gpio_cfg = true, \
351 .skip_psel_cfg = true, \
352 .base_clock = NRF_PWM_CLK_1MHz, \
353 .count_mode = (PWM_PROP(idx, center_aligned) \
354 ? NRF_PWM_MODE_UP_AND_DOWN \
355 : NRF_PWM_MODE_UP), \
356 .top_value = 1000, \
357 .load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
358 .step_mode = NRF_PWM_STEP_TRIGGERED, \
359 }, \
360 .seq.values.p_raw = pwm_nrfx_##idx##_data.seq_values, \
361 .seq.length = NRF_PWM_CHANNEL_COUNT, \
362 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(PWM(idx)), \
363 }; \
364 static int pwm_nrfx_init##idx(const struct device *dev) \
365 { \
366 ANOMALY_109_IRQ_CONNECT( \
367 DT_IRQN(PWM(idx)), DT_IRQ(PWM(idx), priority), \
368 nrfx_isr, nrfx_pwm_##idx##_irq_handler, 0); \
369 return pwm_nrfx_init(dev); \
370 }; \
371 PM_DEVICE_DT_DEFINE(PWM(idx), pwm_nrfx_pm_action); \
372 DEVICE_DT_DEFINE(PWM(idx), \
373 pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
374 &pwm_nrfx_##idx##_data, \
375 &pwm_nrfx_##idx##_config, \
376 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
377 &pwm_nrfx_drv_api_funcs)
378
379 #ifdef CONFIG_HAS_HW_NRF_PWM0
380 PWM_NRFX_DEVICE(0);
381 #endif
382
383 #ifdef CONFIG_HAS_HW_NRF_PWM1
384 PWM_NRFX_DEVICE(1);
385 #endif
386
387 #ifdef CONFIG_HAS_HW_NRF_PWM2
388 PWM_NRFX_DEVICE(2);
389 #endif
390
391 #ifdef CONFIG_HAS_HW_NRF_PWM3
392 PWM_NRFX_DEVICE(3);
393 #endif
394
