1 /*
2 * Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
3 * Copyright 2020 NXP
4 *
5 * Heavily based on pwm_mcux_ftm.c, which is:
6 * Copyright (c) 2017, NXP
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #define DT_DRV_COMPAT nxp_kinetis_tpm
12
13 #include <zephyr/drivers/clock_control.h>
14 #include <errno.h>
15 #include <zephyr/drivers/pwm.h>
16 #include <soc.h>
17 #include <fsl_tpm.h>
18 #include <fsl_clock.h>
19 #include <zephyr/drivers/pinctrl.h>
20
21 #include <zephyr/logging/log.h>
22
23 LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
24
25 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
26
27 struct mcux_tpm_config {
28 TPM_Type *base;
29 const struct device *clock_dev;
30 clock_control_subsys_t clock_subsys;
31 tpm_clock_source_t tpm_clock_source;
32 tpm_clock_prescale_t prescale;
33 uint8_t channel_count;
34 tpm_pwm_mode_t mode;
35 const struct pinctrl_dev_config *pincfg;
36 };
37
38 struct mcux_tpm_data {
39 uint32_t clock_freq;
40 uint32_t period_cycles;
41 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
42 };
43
mcux_tpm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)44 static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
45 uint32_t period_cycles, uint32_t pulse_cycles,
46 pwm_flags_t flags)
47 {
48 const struct mcux_tpm_config *config = dev->config;
49 struct mcux_tpm_data *data = dev->data;
50 uint8_t duty_cycle;
51
52 if (period_cycles == 0U) {
53 LOG_ERR("Channel can not be set to inactive level");
54 return -ENOTSUP;
55 }
56
57 if (channel >= config->channel_count) {
58 LOG_ERR("Invalid channel");
59 return -ENOTSUP;
60 }
61
62 duty_cycle = pulse_cycles * 100U / period_cycles;
63 data->channel[channel].dutyCyclePercent = duty_cycle;
64
65 if ((flags & PWM_POLARITY_INVERTED) == 0) {
66 data->channel[channel].level = kTPM_HighTrue;
67 } else {
68 data->channel[channel].level = kTPM_LowTrue;
69 }
70
71 LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
72 pulse_cycles, period_cycles, duty_cycle, flags);
73
74 if (period_cycles != data->period_cycles) {
75 uint32_t pwm_freq;
76 status_t status;
77
78 if (data->period_cycles != 0) {
79 /* Only warn when not changing from zero */
80 LOG_WRN("Changing period cycles from %d to %d"
81 " affects all %d channels in %s",
82 data->period_cycles, period_cycles,
83 config->channel_count, dev->name);
84 }
85
86 data->period_cycles = period_cycles;
87
88 pwm_freq = (data->clock_freq >> config->prescale) /
89 period_cycles;
90
91 LOG_DBG("pwm_freq=%d, clock_freq=%d", pwm_freq,
92 data->clock_freq);
93
94 if (pwm_freq == 0U) {
95 LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
96 return -EINVAL;
97 }
98
99 TPM_StopTimer(config->base);
100
101 status = TPM_SetupPwm(config->base, data->channel,
102 config->channel_count, config->mode,
103 pwm_freq, data->clock_freq);
104
105 if (status != kStatus_Success) {
106 LOG_ERR("Could not set up pwm");
107 return -ENOTSUP;
108 }
109 TPM_StartTimer(config->base, config->tpm_clock_source);
110 } else {
111 TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
112 data->channel[channel].level);
113 TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
114 duty_cycle);
115 }
116
117 return 0;
118 }
119
mcux_tpm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)120 static int mcux_tpm_get_cycles_per_sec(const struct device *dev,
121 uint32_t channel, uint64_t *cycles)
122 {
123 const struct mcux_tpm_config *config = dev->config;
124 struct mcux_tpm_data *data = dev->data;
125
126 *cycles = data->clock_freq >> config->prescale;
127
128 return 0;
129 }
130
mcux_tpm_init(const struct device * dev)131 static int mcux_tpm_init(const struct device *dev)
132 {
133 const struct mcux_tpm_config *config = dev->config;
134 struct mcux_tpm_data *data = dev->data;
135 tpm_chnl_pwm_signal_param_t *channel = data->channel;
136 tpm_config_t tpm_config;
137 int i;
138 int err;
139
140 if (config->channel_count > ARRAY_SIZE(data->channel)) {
141 LOG_ERR("Invalid channel count");
142 return -EINVAL;
143 }
144
145 if (!device_is_ready(config->clock_dev)) {
146 LOG_ERR("clock control device not ready");
147 return -ENODEV;
148 }
149
150 if (clock_control_on(config->clock_dev, config->clock_subsys)) {
151 LOG_ERR("Could not turn on clock");
152 return -EINVAL;
153 }
154
155 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
156 &data->clock_freq)) {
157 LOG_ERR("Could not get clock frequency");
158 return -EINVAL;
159 }
160
161 for (i = 0; i < config->channel_count; i++) {
162 channel->chnlNumber = i;
163 channel->level = kTPM_NoPwmSignal;
164 channel->dutyCyclePercent = 0;
165 channel->firstEdgeDelayPercent = 0;
166 channel++;
167 }
168
169 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
170 if (err) {
171 return err;
172 }
173
174 TPM_GetDefaultConfig(&tpm_config);
175 tpm_config.prescale = config->prescale;
176
177 TPM_Init(config->base, &tpm_config);
178
179 return 0;
180 }
181
182 static const struct pwm_driver_api mcux_tpm_driver_api = {
183 .set_cycles = mcux_tpm_set_cycles,
184 .get_cycles_per_sec = mcux_tpm_get_cycles_per_sec,
185 };
186
187 #define TPM_DEVICE(n) \
188 PINCTRL_DT_INST_DEFINE(n); \
189 static const struct mcux_tpm_config mcux_tpm_config_##n = { \
190 .base = (TPM_Type *) \
191 DT_INST_REG_ADDR(n), \
192 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
193 .clock_subsys = (clock_control_subsys_t) \
194 DT_INST_CLOCKS_CELL(n, name), \
195 .tpm_clock_source = kTPM_SystemClock, \
196 .prescale = kTPM_Prescale_Divide_16, \
197 .channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
198 DT_INST_REG_ADDR(n)), \
199 .mode = kTPM_EdgeAlignedPwm, \
200 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
201 }; \
202 static struct mcux_tpm_data mcux_tpm_data_##n; \
203 DEVICE_DT_INST_DEFINE(n, &mcux_tpm_init, NULL, \
204 &mcux_tpm_data_##n, \
205 &mcux_tpm_config_##n, \
206 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
207 &mcux_tpm_driver_api);
208
209 DT_INST_FOREACH_STATUS_OKAY(TPM_DEVICE)
210
