1 /*
2 * Copyright (c) 2019, Linaro
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_pwm
8
9 #include <errno.h>
10 #include <zephyr/drivers/pwm.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <soc.h>
13 #include <fsl_pwm.h>
14 #include <zephyr/drivers/pinctrl.h>
15
16 #include <zephyr/logging/log.h>
17
18 LOG_MODULE_REGISTER(pwm_mcux, CONFIG_PWM_LOG_LEVEL);
19
20 #define CHANNEL_COUNT 2
21
22 struct pwm_mcux_config {
23 PWM_Type *base;
24 uint8_t index;
25 const struct device *clock_dev;
26 clock_control_subsys_t clock_subsys;
27 pwm_clock_prescale_t prescale;
28 pwm_register_reload_t reload;
29 pwm_mode_t mode;
30 bool run_wait;
31 bool run_debug;
32 const struct pinctrl_dev_config *pincfg;
33 };
34
35 struct pwm_mcux_data {
36 uint32_t period_cycles[CHANNEL_COUNT];
37 pwm_signal_param_t channel[CHANNEL_COUNT];
38 };
39
mcux_pwm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)40 static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel,
41 uint32_t period_cycles, uint32_t pulse_cycles,
42 pwm_flags_t flags)
43 {
44 const struct pwm_mcux_config *config = dev->config;
45 struct pwm_mcux_data *data = dev->data;
46 pwm_level_select_t level;
47
48 if (channel >= CHANNEL_COUNT) {
49 LOG_ERR("Invalid channel");
50 return -EINVAL;
51 }
52
53 if (period_cycles == 0) {
54 LOG_ERR("Channel can not be set to inactive level");
55 return -ENOTSUP;
56 }
57
58 if (period_cycles > UINT16_MAX) {
59 /* 16-bit resolution */
60 LOG_ERR("Too long period (%u), adjust pwm prescaler!",
61 period_cycles);
62 /* TODO: dynamically adjust prescaler */
63 return -EINVAL;
64 }
65
66 if (flags & PWM_POLARITY_INVERTED) {
67 level = kPWM_LowTrue;
68 } else {
69 level = kPWM_HighTrue;
70 }
71
72 if (period_cycles != data->period_cycles[channel]
73 || level != data->channel[channel].level) {
74 uint32_t clock_freq;
75 status_t status;
76
77 data->period_cycles[channel] = period_cycles;
78
79 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
80 &clock_freq)) {
81 return -EINVAL;
82 }
83
84 data->channel[channel].pwmchannelenable = true;
85
86 PWM_StopTimer(config->base, 1U << config->index);
87
88 /*
89 * We will directly write the duty cycle pulse width
90 * and full pulse width into the VALx registers to
91 * setup PWM with higher resolution.
92 * Therefore we use dummy values for the duty cycle
93 * and frequency.
94 */
95 data->channel[channel].dutyCyclePercent = 0;
96 data->channel[channel].level = level;
97
98 status = PWM_SetupPwm(config->base, config->index,
99 &data->channel[channel], 1U,
100 config->mode, 1U, clock_freq);
101 if (status != kStatus_Success) {
102 LOG_ERR("Could not set up pwm");
103 return -ENOTSUP;
104 }
105
106 /* Setup VALx values directly for edge aligned PWM */
107 if (channel == 0) {
108 /* Side A */
109 PWM_SetVALxValue(config->base, config->index,
110 kPWM_ValueRegister_0,
111 (uint16_t)(period_cycles / 2U));
112 PWM_SetVALxValue(config->base, config->index,
113 kPWM_ValueRegister_1,
114 (uint16_t)(period_cycles - 1U));
115 PWM_SetVALxValue(config->base, config->index,
116 kPWM_ValueRegister_2, 0U);
117 PWM_SetVALxValue(config->base, config->index,
118 kPWM_ValueRegister_3,
119 (uint16_t)pulse_cycles);
120 } else {
121 /* Side B */
122 PWM_SetVALxValue(config->base, config->index,
123 kPWM_ValueRegister_0,
124 (uint16_t)(period_cycles / 2U));
125 PWM_SetVALxValue(config->base, config->index,
126 kPWM_ValueRegister_1,
127 (uint16_t)(period_cycles - 1U));
128 PWM_SetVALxValue(config->base, config->index,
129 kPWM_ValueRegister_4, 0U);
130 PWM_SetVALxValue(config->base, config->index,
131 kPWM_ValueRegister_5,
132 (uint16_t)pulse_cycles);
133 }
134
135 PWM_SetPwmLdok(config->base, 1U << config->index, true);
136
137 PWM_StartTimer(config->base, 1U << config->index);
138 } else {
139 /* Setup VALx values directly for edge aligned PWM */
140 if (channel == 0) {
141 /* Side A */
142 PWM_SetVALxValue(config->base, config->index,
143 kPWM_ValueRegister_2, 0U);
144 PWM_SetVALxValue(config->base, config->index,
145 kPWM_ValueRegister_3,
146 (uint16_t)pulse_cycles);
147 } else {
148 /* Side B */
149 PWM_SetVALxValue(config->base, config->index,
150 kPWM_ValueRegister_4, 0U);
151 PWM_SetVALxValue(config->base, config->index,
152 kPWM_ValueRegister_5,
153 (uint16_t)pulse_cycles);
154 }
155 PWM_SetPwmLdok(config->base, 1U << config->index, true);
156 }
157
158 return 0;
159 }
160
mcux_pwm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)161 static int mcux_pwm_get_cycles_per_sec(const struct device *dev,
162 uint32_t channel, uint64_t *cycles)
163 {
164 const struct pwm_mcux_config *config = dev->config;
165 uint32_t clock_freq;
166
167 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
168 &clock_freq)) {
169 return -EINVAL;
170 }
171 *cycles = clock_freq >> config->prescale;
172
173 return 0;
174 }
175
pwm_mcux_init(const struct device * dev)176 static int pwm_mcux_init(const struct device *dev)
177 {
178 const struct pwm_mcux_config *config = dev->config;
179 struct pwm_mcux_data *data = dev->data;
180 pwm_config_t pwm_config;
181 status_t status;
182 int i, err;
183
184 if (!device_is_ready(config->clock_dev)) {
185 LOG_ERR("clock control device not ready");
186 return -ENODEV;
187 }
188
189 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
190 if (err < 0) {
191 return err;
192 }
193
194 LOG_DBG("Set prescaler %d, reload mode %d",
195 1 << config->prescale, config->reload);
196
197 PWM_GetDefaultConfig(&pwm_config);
198 pwm_config.prescale = config->prescale;
199 pwm_config.reloadLogic = config->reload;
200 pwm_config.clockSource = kPWM_BusClock;
201 pwm_config.enableDebugMode = config->run_debug;
202 #if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN)
203 pwm_config.enableWait = config->run_wait;
204 #endif
205
206 status = PWM_Init(config->base, config->index, &pwm_config);
207 if (status != kStatus_Success) {
208 LOG_ERR("Unable to init PWM");
209 return -EIO;
210 }
211
212 /* Disable fault sources */
213 for (i = 0; i < FSL_FEATURE_PWM_FAULT_CH_COUNT; i++) {
214 config->base->SM[config->index].DISMAP[i] = 0x0000;
215 }
216
217 data->channel[0].pwmChannel = kPWM_PwmA;
218 data->channel[0].level = kPWM_HighTrue;
219 data->channel[1].pwmChannel = kPWM_PwmB;
220 data->channel[1].level = kPWM_HighTrue;
221
222 return 0;
223 }
224
225 static const struct pwm_driver_api pwm_mcux_driver_api = {
226 .set_cycles = mcux_pwm_set_cycles,
227 .get_cycles_per_sec = mcux_pwm_get_cycles_per_sec,
228 };
229
230 #define PWM_DEVICE_INIT_MCUX(n) \
231 static struct pwm_mcux_data pwm_mcux_data_ ## n; \
232 PINCTRL_DT_INST_DEFINE(n); \
233 \
234 static const struct pwm_mcux_config pwm_mcux_config_ ## n = { \
235 .base = (PWM_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
236 .index = DT_INST_PROP(n, index), \
237 .mode = kPWM_EdgeAligned, \
238 .prescale = _CONCAT(kPWM_Prescale_Divide_, DT_INST_PROP(n, nxp_prescaler)),\
239 .reload = DT_ENUM_IDX_OR(DT_DRV_INST(n), nxp_reload,\
240 kPWM_ReloadPwmFullCycle),\
241 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
242 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
243 .run_wait = DT_INST_PROP(n, run_in_wait), \
244 .run_debug = DT_INST_PROP(n, run_in_debug), \
245 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
246 }; \
247 \
248 DEVICE_DT_INST_DEFINE(n, \
249 pwm_mcux_init, \
250 NULL, \
251 &pwm_mcux_data_ ## n, \
252 &pwm_mcux_config_ ## n, \
253 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
254 &pwm_mcux_driver_api);
255
256 DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT_MCUX)
257
