1 /*
2 * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_pwm
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/pwm.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
13 #include <errno.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <soc_dt.h>
17 #include <stdlib.h>
18
19 #include <zephyr/logging/log.h>
20
21 LOG_MODULE_REGISTER(pwm_ite_it8xxx2, CONFIG_PWM_LOG_LEVEL);
22
23 #define PWM_CTRX_MIN 100
24 #define PWM_FREQ EC_FREQ
25 #define PCSSG_MASK 0x3
26
27 struct pwm_it8xxx2_cfg {
28 /* PWM channel duty cycle register */
29 uintptr_t reg_dcr;
30 /* PWM channel clock source selection register */
31 uintptr_t reg_pcssg;
32 /* PWM channel clock source gating register */
33 uintptr_t reg_pcsgr;
34 /* PWM channel output polarity register */
35 uintptr_t reg_pwmpol;
36 /* PWM channel */
37 int channel;
38 /* PWM prescaler control register base */
39 struct pwm_it8xxx2_regs *base;
40 /* Select PWM prescaler that output to PWM channel */
41 int prs_sel;
42 /* PWM alternate configuration */
43 const struct pinctrl_dev_config *pcfg;
44 };
45
pwm_enable(const struct device * dev,int enabled)46 static void pwm_enable(const struct device *dev, int enabled)
47 {
48 const struct pwm_it8xxx2_cfg *config = dev->config;
49 volatile uint8_t *reg_pcsgr = (uint8_t *)config->reg_pcsgr;
50 int ch = config->channel;
51
52 if (enabled) {
53 /* PWM channel clock source not gating */
54 *reg_pcsgr &= ~BIT(ch);
55 } else {
56 /* PWM channel clock source gating */
57 *reg_pcsgr |= BIT(ch);
58 }
59 }
60
pwm_it8xxx2_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)61 static int pwm_it8xxx2_get_cycles_per_sec(const struct device *dev,
62 uint32_t channel, uint64_t *cycles)
63 {
64 ARG_UNUSED(channel);
65
66 /*
67 * There are three ways to call pwm_it8xxx2_set_cycles() from pwm api:
68 * 1) pwm_set_cycles_usec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
69 * target_freq = pwm_clk_src / period_cycles
70 * = cycles / (period * cycles / USEC_PER_SEC)
71 * = USEC_PER_SEC / period
72 * 2) pwm_set_cycles_nsec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
73 * target_freq = pwm_clk_src / period_cycles
74 * = cycles / (period * cycles / NSEC_PER_SEC)
75 * = NSEC_PER_SEC / period
76 * 3) pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles()
77 * target_freq = pwm_clk_src / period_cycles
78 * = cycles / period
79 *
80 * If we need to pwm output in EC power saving mode, then we will switch
81 * the prescaler clock source (cycles) from 8MHz to 32.768kHz. In order
82 * to get the same target_freq in the 3) case, we always return PWM_FREQ.
83 */
84 *cycles = (uint64_t) PWM_FREQ;
85
86 return 0;
87 }
88
pwm_it8xxx2_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)89 static int pwm_it8xxx2_set_cycles(const struct device *dev,
90 uint32_t channel, uint32_t period_cycles,
91 uint32_t pulse_cycles, pwm_flags_t flags)
92 {
93 const struct pwm_it8xxx2_cfg *config = dev->config;
94 struct pwm_it8xxx2_regs *const inst = config->base;
95 volatile uint8_t *reg_dcr = (uint8_t *)config->reg_dcr;
96 volatile uint8_t *reg_pwmpol = (uint8_t *)config->reg_pwmpol;
97 int ch = config->channel;
98 int prs_sel = config->prs_sel;
99 uint32_t actual_freq = 0xffffffff, target_freq, deviation, cxcprs, ctr;
100 uint64_t pwm_clk_src;
101
102 /* Select PWM inverted polarity (ex. active-low pulse) */
103 if (flags & PWM_POLARITY_INVERTED) {
104 *reg_pwmpol |= BIT(ch);
105 } else {
106 *reg_pwmpol &= ~BIT(ch);
107 }
108
109 /* Enable PWM output open-drain */
110 if (flags & PWM_IT8XXX2_OPEN_DRAIN) {
111 inst->PWMODENR |= BIT(ch);
112 }
113
114 /* If pulse cycles is 0, set duty cycle 0 and enable pwm channel */
115 if (pulse_cycles == 0) {
116 *reg_dcr = 0;
117 pwm_enable(dev, 1);
118 return 0;
119 }
120
121 pwm_it8xxx2_get_cycles_per_sec(dev, channel, &pwm_clk_src);
122 target_freq = ((uint32_t) pwm_clk_src) / period_cycles;
123
124 /*
125 * Support PWM output frequency:
126 * 1) 8MHz clock source: 1Hz <= target_freq <= 79207Hz
127 * 2) 32.768KHz clock source: 1Hz <= target_freq <= 324Hz
128 * NOTE: PWM output signal maximum supported frequency comes from
129 * [8MHz or 32.768KHz] / 1 / (PWM_CTRX_MIN + 1).
130 * PWM output signal minimum supported frequency comes from
131 * [8MHz or 32.768KHz] / 65536 / 256, the minimum integer is 1.
132 */
133 if (target_freq < 1) {
134 LOG_ERR("PWM output frequency is < 1 !");
135 return -EINVAL;
136 }
137
138 deviation = (target_freq / 100) + 1;
139
140 /*
141 * Default clock source setting is 8MHz, when ITE chip is in power
142 * saving mode, clock source 8MHz will be gated (32.768KHz won't).
143 * So if we still need pwm output in mode, then we should set frequency
144 * <=324Hz in board dts. Now change prescaler clock source from 8MHz to
145 * 32.768KHz to support pwm output in mode.
146 */
147 if (target_freq <= 324) {
148 if (inst->PCFSR & BIT(prs_sel)) {
149 inst->PCFSR &= ~BIT(prs_sel);
150 }
151
152 pwm_clk_src = (uint64_t) 32768;
153 }
154
155 /*
156 * PWM output signal frequency is
157 * pwm_clk_src / ((CxCPRS[15:0] + 1) * (CTRx[7:0] + 1))
158 * NOTE: 1) define CTR minimum is 100 for more precisely when
159 * calculate DCR
160 * 2) CxCPRS[15:0] value 0001h results in a divisor 2
161 * CxCPRS[15:0] value FFFFh results in a divisor 65536
162 * CTRx[7:0] value 00h results in a divisor 1
163 * CTRx[7:0] value FFh results in a divisor 256
164 */
165 for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) {
166 cxcprs = (((uint32_t) pwm_clk_src) / (ctr + 1) / target_freq);
167 /*
168 * Make sure cxcprs isn't zero, or we will have
169 * divide-by-zero on calculating actual_freq.
170 */
171 if (cxcprs != 0) {
172 actual_freq = ((uint32_t) pwm_clk_src) / (ctr + 1) / cxcprs;
173 if (abs(actual_freq - target_freq) < deviation) {
174 /* CxCPRS[15:0] = cxcprs - 1 */
175 cxcprs--;
176 break;
177 }
178 }
179 }
180
181 if (cxcprs > UINT16_MAX) {
182 LOG_ERR("PWM prescaler CxCPRS only support 2 bytes !");
183 return -EINVAL;
184 }
185
186 /* Set PWM prescaler clock divide and cycle time register */
187 if (prs_sel == PWM_PRESCALER_C4) {
188 inst->C4CPRS = cxcprs & 0xFF;
189 inst->C4MCPRS = (cxcprs >> 8) & 0xFF;
190 inst->CTR1 = ctr;
191 } else if (prs_sel == PWM_PRESCALER_C6) {
192 inst->C6CPRS = cxcprs & 0xFF;
193 inst->C6MCPRS = (cxcprs >> 8) & 0xFF;
194 inst->CTR2 = ctr;
195 } else if (prs_sel == PWM_PRESCALER_C7) {
196 inst->C7CPRS = cxcprs & 0xFF;
197 inst->C7MCPRS = (cxcprs >> 8) & 0xFF;
198 inst->CTR3 = ctr;
199 }
200
201 /* Set PWM channel duty cycle register */
202 *reg_dcr = (ctr * pulse_cycles) / period_cycles;
203
204 /* PWM channel clock source not gating */
205 pwm_enable(dev, 1);
206
207 LOG_DBG("clock source freq %d, target freq %d",
208 (uint32_t) pwm_clk_src, target_freq);
209
210 return 0;
211 }
212
pwm_it8xxx2_init(const struct device * dev)213 static int pwm_it8xxx2_init(const struct device *dev)
214 {
215 const struct pwm_it8xxx2_cfg *config = dev->config;
216 struct pwm_it8xxx2_regs *const inst = config->base;
217 volatile uint8_t *reg_pcssg = (uint8_t *)config->reg_pcssg;
218 int ch = config->channel;
219 int prs_sel = config->prs_sel;
220 int pcssg_shift;
221 int pcssg_mask;
222 int status;
223
224 /* PWM channel clock source gating before configuring */
225 pwm_enable(dev, 0);
226
227 /* Select clock source 8MHz for prescaler */
228 inst->PCFSR |= BIT(prs_sel);
229
230 /* Bit shift and mask of prescaler clock source select group register */
231 pcssg_shift = (ch % 4) * 2;
232 pcssg_mask = (prs_sel & PCSSG_MASK) << pcssg_shift;
233
234 /* Select which prescaler output to PWM channel */
235 *reg_pcssg &= ~(PCSSG_MASK << pcssg_shift);
236 *reg_pcssg |= pcssg_mask;
237
238 /*
239 * The cycle timer1 of it8320 later series was enhanced from
240 * 8bits to 10bits resolution, and others are still 8bit resolution.
241 * Because the cycle timer1 high byte default value is not zero,
242 * we clear cycle timer1 high byte at init and use it as 8-bit
243 * resolution like others.
244 */
245 inst->CTR1M = 0;
246
247 /* Enable PWMs clock counter */
248 inst->ZTIER |= IT8XXX2_PWM_PCCE;
249
250 /* Set alternate mode of PWM pin */
251 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
252 if (status < 0) {
253 LOG_ERR("Failed to configure PWM pins");
254 return status;
255 }
256
257 return 0;
258 }
259
260 static const struct pwm_driver_api pwm_it8xxx2_api = {
261 .set_cycles = pwm_it8xxx2_set_cycles,
262 .get_cycles_per_sec = pwm_it8xxx2_get_cycles_per_sec,
263 };
264
265 /* Device Instance */
266 #define PWM_IT8XXX2_INIT(inst) \
267 PINCTRL_DT_INST_DEFINE(inst); \
268 \
269 static const struct pwm_it8xxx2_cfg pwm_it8xxx2_cfg_##inst = { \
270 .reg_dcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
271 .reg_pcssg = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
272 .reg_pcsgr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
273 .reg_pwmpol = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
274 .channel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), channel), \
275 .base = (struct pwm_it8xxx2_regs *) DT_REG_ADDR(DT_NODELABEL(prs)), \
276 .prs_sel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), prescaler_cx), \
277 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
278 }; \
279 \
280 DEVICE_DT_INST_DEFINE(inst, \
281 &pwm_it8xxx2_init, \
282 NULL, \
283 NULL, \
284 &pwm_it8xxx2_cfg_##inst, \
285 PRE_KERNEL_1, \
286 CONFIG_PWM_INIT_PRIORITY, \
287 &pwm_it8xxx2_api);
288
289 DT_INST_FOREACH_STATUS_OKAY(PWM_IT8XXX2_INIT)
290
