1 /*
2 * Copyright (c) 2023 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT intel_blinky_pwm
8
9 #include <errno.h>
10 #include <soc.h>
11 #include <zephyr/device.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/init.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/devicetree.h>
16 #include <zephyr/drivers/pwm.h>
17
18 #define PWM_ENABLE 0x80000000
19 #define PWM_SWUP 0x40000000
20 #define PWM_FREQ_INT_SHIFT 8
21 #define PWM_BASE_UNIT_FRACTION 14
22 #define PWM_FREQ_MAX 0x100
23 #define PWM_DUTY_MAX 0x100
24
25 struct bk_intel_config {
26 DEVICE_MMIO_NAMED_ROM(reg_base);
27 uint32_t reg_offset;
28 uint32_t clock_freq;
29 uint32_t max_pins;
30 };
31
32 struct bk_intel_runtime {
33 DEVICE_MMIO_NAMED_RAM(reg_base);
34 };
35
bk_intel_set_cycles(const struct device * dev,uint32_t pin,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)36 static int bk_intel_set_cycles(const struct device *dev, uint32_t pin,
37 uint32_t period_cycles, uint32_t pulse_cycles,
38 pwm_flags_t flags)
39 {
40 struct bk_intel_runtime *rt = dev->data;
41 const struct bk_intel_config *cfg = dev->config;
42 uint32_t ret = 0;
43 uint32_t val = 0;
44 uint32_t duty;
45 float period;
46 float out_freq;
47 uint32_t base_unit;
48
49 if (pin >= cfg->max_pins) {
50 ret = -EINVAL;
51 goto err;
52 }
53
54 out_freq = cfg->clock_freq / (float) period_cycles;
55 period = (out_freq * PWM_FREQ_MAX) / cfg->clock_freq;
56 base_unit = (uint32_t) (period * (1 << PWM_BASE_UNIT_FRACTION));
57 duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles;
58
59 if (duty) {
60 val = PWM_DUTY_MAX - duty;
61 val |= (base_unit << PWM_FREQ_INT_SHIFT);
62 } else {
63 val = PWM_DUTY_MAX - 1;
64 }
65
66 val |= PWM_ENABLE | PWM_SWUP;
67
68 if (period >= PWM_FREQ_MAX) {
69 ret = -EINVAL;
70 goto err;
71 }
72
73 if (duty > PWM_DUTY_MAX) {
74 ret = -EINVAL;
75 goto err;
76 }
77
78 sys_write32(val, rt->reg_base + cfg->reg_offset);
79 err:
80 return ret;
81 }
82
bk_intel_get_cycles_per_sec(const struct device * dev,uint32_t pin,uint64_t * cycles)83 static int bk_intel_get_cycles_per_sec(const struct device *dev, uint32_t pin,
84 uint64_t *cycles)
85 {
86 const struct bk_intel_config *cfg = dev->config;
87
88 if (pin >= cfg->max_pins) {
89 return -EINVAL;
90 }
91
92 *cycles = cfg->clock_freq;
93
94 return 0;
95 }
96
97 static const struct pwm_driver_api api_funcs = {
98 .set_cycles = bk_intel_set_cycles,
99 .get_cycles_per_sec = bk_intel_get_cycles_per_sec,
100 };
101
bk_intel_init(const struct device * dev)102 static int bk_intel_init(const struct device *dev)
103 {
104 struct bk_intel_runtime *runtime = dev->data;
105 const struct bk_intel_config *config = dev->config;
106
107 device_map(&runtime->reg_base,
108 config->reg_base.phys_addr & ~0xFFU,
109 config->reg_base.size,
110 K_MEM_CACHE_NONE);
111
112 return 0;
113 }
114
115 #define BK_INTEL_DEV_CFG(n) \
116 static const struct bk_intel_config bk_cfg_##n = { \
117 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
118 .reg_offset = DT_INST_PROP(n, reg_offset), \
119 .max_pins = DT_INST_PROP(n, max_pins), \
120 .clock_freq = DT_INST_PROP(n, clock_frequency), \
121 }; \
122 \
123 static struct bk_intel_runtime bk_rt_##n; \
124 DEVICE_DT_INST_DEFINE(n, &bk_intel_init, NULL, \
125 &bk_rt_##n, &bk_cfg_##n, \
126 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
127 &api_funcs); \
128
129 DT_INST_FOREACH_STATUS_OKAY(BK_INTEL_DEV_CFG)
130
