1 /*
2 * Copyright (c) 2023 Zephyr Project
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_cc13xx_cc26xx_timer_pwm
8
9 #include <zephyr/drivers/i2c.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/drivers/pwm.h>
12
13 #include <driverlib/gpio.h>
14 #include <driverlib/prcm.h>
15 #include <driverlib/timer.h>
16 #include <inc/hw_memmap.h>
17 #include <inc/hw_types.h>
18 #include <ti/drivers/Power.h>
19 #include <ti/drivers/power/PowerCC26XX.h>
20
21 #include <zephyr/logging/log.h>
22 #define LOG_MODULE_NAME pwm_cc13xx_cc26xx_timer
23 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
24
25 /* TODO: Clock frequency can be settable via KConfig, see TOP:PRCM:GPTCLKDIV */
26 #define CPU_FREQ ((uint32_t)DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency))
27
28 /* GPT peripherals in 16 bit mode have maximum 24 counter bits incl. the
29 * prescaler. Count is set to (2^24 - 2) to allow for a glitch free 100% duty
30 * cycle at max. period count.
31 */
32 #define PWM_COUNT_MAX 0xFFFFFE
33 #define PWM_INITIAL_PERIOD PWM_COUNT_MAX
34 #define PWM_INITIAL_DUTY 0U /* initially off */
35
36 struct pwm_cc13xx_cc26xx_data {
37 };
38
39 struct pwm_cc13xx_cc26xx_config {
40 const uint32_t gpt_base; /* GPT register base address */
41 const struct pinctrl_dev_config *pcfg;
42
43 LOG_INSTANCE_PTR_DECLARE(log);
44 };
45
write_value(const struct pwm_cc13xx_cc26xx_config * config,uint32_t value,uint32_t prescale_register,uint32_t value_register)46 static void write_value(const struct pwm_cc13xx_cc26xx_config *config, uint32_t value,
47 uint32_t prescale_register, uint32_t value_register)
48 {
49 /* Upper byte represents the prescaler value. */
50 uint8_t prescaleValue = 0xff & (value >> 16);
51
52 HWREG(config->gpt_base + prescale_register) = prescaleValue;
53
54 /* The remaining bytes represent the load / match value. */
55 HWREG(config->gpt_base + value_register) = value & 0xffff;
56 }
57
set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config * config,uint32_t period,uint32_t pulse)58 static int set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config *config, uint32_t period,
59 uint32_t pulse)
60 {
61 uint32_t match_value = pulse;
62
63 if (pulse == 0U) {
64 TimerDisable(config->gpt_base, TIMER_B);
65 #ifdef CONFIG_PM
66 Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY);
67 #endif
68 match_value = period + 1;
69 }
70
71 /* Fail if period is out of range */
72 if ((period > PWM_COUNT_MAX) || (period == 0)) {
73 LOG_ERR("Period (%d) is out of range.", period);
74 return -EINVAL;
75 }
76
77 /* Compare to new period and fail if invalid */
78 if (period < (match_value - 1) || (match_value < 0)) {
79 LOG_ERR("Period (%d) is shorter than pulse (%d).", period, pulse);
80 return -EINVAL;
81 }
82
83 /* Store new period and update timer */
84 write_value(config, period, GPT_O_TBPR, GPT_O_TBILR);
85 write_value(config, match_value, GPT_O_TBPMR, GPT_O_TBMATCHR);
86
87 if (pulse > 0U) {
88 #ifdef CONFIG_PM
89 Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY);
90 #endif
91 TimerEnable(config->gpt_base, TIMER_B);
92 }
93
94 LOG_DBG("Period and pulse successfully set.");
95 return 0;
96 }
97
set_cycles(const struct device * dev,uint32_t channel,uint32_t period,uint32_t pulse,pwm_flags_t flags)98 static int set_cycles(const struct device *dev, uint32_t channel, uint32_t period, uint32_t pulse,
99 pwm_flags_t flags)
100 {
101 const struct pwm_cc13xx_cc26xx_config *config = dev->config;
102
103 if (channel != 0) {
104 return -EIO;
105 }
106
107 set_period_and_pulse(config, period, pulse);
108
109 return 0;
110 }
111
get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)112 static int get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
113 {
114 if (channel > 0) {
115 return -EIO;
116 }
117
118 if (cycles) {
119 *cycles = CPU_FREQ;
120 }
121
122 return 0;
123 }
124
125 static const struct pwm_driver_api pwm_driver_api = {
126 .set_cycles = set_cycles,
127 .get_cycles_per_sec = get_cycles_per_sec,
128 };
129
130 #ifdef CONFIG_PM
get_timer_inst_number(const struct pwm_cc13xx_cc26xx_config * config)131 static int get_timer_inst_number(const struct pwm_cc13xx_cc26xx_config *config)
132 {
133 switch (config->gpt_base) {
134 case GPT0_BASE:
135 return 0;
136 case GPT1_BASE:
137 return 1;
138 case GPT2_BASE:
139 return 2;
140 case GPT3_BASE:
141 return 3;
142 default:
143 __ASSERT_UNREACHABLE;
144 }
145 }
146 #else
get_timer_peripheral(const struct pwm_cc13xx_cc26xx_config * config)147 static int get_timer_peripheral(const struct pwm_cc13xx_cc26xx_config *config)
148 {
149 switch (config->gpt_base) {
150 case GPT0_BASE:
151 return PRCM_PERIPH_TIMER0;
152 case GPT1_BASE:
153 return PRCM_PERIPH_TIMER1;
154 case GPT2_BASE:
155 return PRCM_PERIPH_TIMER2;
156 case GPT3_BASE:
157 return PRCM_PERIPH_TIMER3;
158 default:
159 __ASSERT_UNREACHABLE;
160 }
161 }
162 #endif /* CONFIG_PM */
163
init_pwm(const struct device * dev)164 static int init_pwm(const struct device *dev)
165 {
166 const struct pwm_cc13xx_cc26xx_config *config = dev->config;
167 pinctrl_soc_pin_t pin = config->pcfg->states[0].pins[0];
168 int ret;
169
170 #ifdef CONFIG_PM
171 /* Set dependency on gpio resource to turn on power domains */
172 Power_setDependency(get_timer_inst_number(config));
173 #else
174 /* Enable peripheral power domain. */
175 PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
176
177 /* Enable GPIO peripheral. */
178 PRCMPeripheralRunEnable(get_timer_peripheral(config));
179
180 /* Load PRCM settings. */
181 PRCMLoadSet();
182 while (!PRCMLoadGet()) {
183 continue;
184 }
185 #endif /* CONFIG_PM */
186
187 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
188 if (ret < 0) {
189 LOG_ERR("failed to setup PWM pinctrl");
190 return ret;
191 }
192
193 /* Configures the PWM idle output level.
194 *
195 * TODO: Make PWM idle high/low configurable via custom DT PWM flag.
196 */
197 GPIO_writeDio(pin.pin, 0);
198
199 GPIO_setOutputEnableDio(pin.pin, GPIO_OUTPUT_ENABLE);
200
201 /* Peripheral should not be accessed until power domain is on. */
202 while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON) {
203 continue;
204 }
205
206 TimerDisable(config->gpt_base, TIMER_B);
207
208 HWREG(config->gpt_base + GPT_O_CFG) = GPT_CFG_CFG_16BIT_TIMER;
209 /* Stall timer when debugging.
210 *
211 * TODO: Make debug stall configurable via custom DT prop.
212 */
213 HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBSTALL;
214
215 /* TODO: Make PWM polarity configurable via DT PWM flag. */
216 HWREG(config->gpt_base + GPT_O_TBMR) = GPT_TBMR_TBAMS_PWM | GPT_TBMR_TBMRSU_TOUPDATE |
217 GPT_TBMR_TBPWMIE_EN | GPT_TBMR_TBMR_PERIODIC;
218
219 set_period_and_pulse(config, PWM_INITIAL_PERIOD, PWM_INITIAL_DUTY);
220
221 return 0;
222 }
223
224 #define DT_TIMER(idx) DT_INST_PARENT(idx)
225 #define DT_TIMER_BASE_ADDR(idx) (DT_REG_ADDR(DT_TIMER(idx)))
226
227 #define PWM_DEVICE_INIT(idx) \
228 PINCTRL_DT_INST_DEFINE(idx); \
229 LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_PWM_LOG_LEVEL); \
230 static const struct pwm_cc13xx_cc26xx_config pwm_cc13xx_cc26xx_##idx##_config = { \
231 .gpt_base = DT_TIMER_BASE_ADDR(idx), \
232 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
233 LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx)}; \
234 \
235 static struct pwm_cc13xx_cc26xx_data pwm_cc13xx_cc26xx_##idx##_data; \
236 \
237 DEVICE_DT_INST_DEFINE(idx, init_pwm, NULL, &pwm_cc13xx_cc26xx_##idx##_data, \
238 &pwm_cc13xx_cc26xx_##idx##_config, POST_KERNEL, \
239 CONFIG_PWM_INIT_PRIORITY, &pwm_driver_api)
240
241 DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT);
242
