1 /*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT telink_b91_pwm
8
9 #include <pwm.h>
10 #include <clock.h>
11 #include <zephyr/drivers/pwm.h>
12 #include <zephyr/drivers/pinctrl.h>
13
14 struct pwm_b91_config {
15 const struct pinctrl_dev_config *pcfg;
16 uint32_t clock_frequency;
17 uint8_t channels;
18 uint8_t clk32k_ch_enable;
19 };
20
21 /* API implementation: init */
pwm_b91_init(const struct device * dev)22 static int pwm_b91_init(const struct device *dev)
23 {
24 const struct pwm_b91_config *config = dev->config;
25
26 uint32_t status = 0;
27 uint8_t clk_32k_en = 0;
28 uint32_t pwm_clk_div = 0;
29
30 /* Calculate and check PWM clock divider */
31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1;
32 if (pwm_clk_div > 255) {
33 return -EINVAL;
34 }
35
36 /* Set PWM Peripheral clock */
37 pwm_set_clk((unsigned char) (pwm_clk_div & 0xFF));
38
39 /* Set PWM 32k Channel clock if enabled */
40 clk_32k_en |= (config->clk32k_ch_enable & BIT(0)) ? PWM_CLOCK_32K_CHN_PWM0 : 0;
41 clk_32k_en |= (config->clk32k_ch_enable & BIT(1)) ? PWM_CLOCK_32K_CHN_PWM1 : 0;
42 clk_32k_en |= (config->clk32k_ch_enable & BIT(2)) ? PWM_CLOCK_32K_CHN_PWM2 : 0;
43 clk_32k_en |= (config->clk32k_ch_enable & BIT(3)) ? PWM_CLOCK_32K_CHN_PWM3 : 0;
44 clk_32k_en |= (config->clk32k_ch_enable & BIT(4)) ? PWM_CLOCK_32K_CHN_PWM4 : 0;
45 clk_32k_en |= (config->clk32k_ch_enable & BIT(5)) ? PWM_CLOCK_32K_CHN_PWM5 : 0;
46 pwm_32k_chn_en(clk_32k_en);
47
48 /* Config PWM pins */
49 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
50 if (status < 0) {
51 return status;
52 }
53
54 return 0;
55 }
56
57 /* API implementation: set_cycles */
pwm_b91_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)58 static int pwm_b91_set_cycles(const struct device *dev, uint32_t channel,
59 uint32_t period_cycles, uint32_t pulse_cycles,
60 pwm_flags_t flags)
61 {
62 const struct pwm_b91_config *config = dev->config;
63
64 /* check pwm channel */
65 if (channel >= config->channels) {
66 return -EINVAL;
67 }
68
69 /* check size of pulse and period (2 bytes) */
70 if ((period_cycles > 0xFFFFu) ||
71 (pulse_cycles > 0xFFFFu)) {
72 return -EINVAL;
73 }
74
75 /* set polarity */
76 if (flags & PWM_POLARITY_INVERTED) {
77 pwm_invert_en(channel);
78 } else {
79 pwm_invert_dis(channel);
80 }
81
82 /* set pulse and period */
83 pwm_set_tcmp(channel, pulse_cycles);
84 pwm_set_tmax(channel, period_cycles);
85
86 /* start pwm */
87 pwm_start(channel);
88
89 return 0;
90 }
91
92 /* API implementation: get_cycles_per_sec */
pwm_b91_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)93 static int pwm_b91_get_cycles_per_sec(const struct device *dev,
94 uint32_t channel, uint64_t *cycles)
95 {
96 const struct pwm_b91_config *config = dev->config;
97
98 /* check pwm channel */
99 if (channel >= config->channels) {
100 return -EINVAL;
101 }
102
103 if ((config->clk32k_ch_enable & BIT(channel)) != 0U) {
104 *cycles = 32000u;
105 } else {
106 *cycles = sys_clk.pclk * 1000 * 1000 / (reg_pwm_clkdiv + 1);
107 }
108
109 return 0;
110 }
111
112 /* PWM driver APIs structure */
113 static const struct pwm_driver_api pwm_b91_driver_api = {
114 .set_cycles = pwm_b91_set_cycles,
115 .get_cycles_per_sec = pwm_b91_get_cycles_per_sec,
116 };
117
118 /* PWM driver registration */
119 #define PWM_B91_INIT(n) \
120 PINCTRL_DT_INST_DEFINE(n); \
121 \
122 static const struct pwm_b91_config config##n = { \
123 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
124 .clock_frequency = DT_INST_PROP(n, clock_frequency), \
125 .channels = DT_INST_PROP(n, channels), \
126 .clk32k_ch_enable = \
127 ((DT_INST_PROP(n, clk32k_ch0_enable) << 0U) | \
128 (DT_INST_PROP(n, clk32k_ch1_enable) << 1U) | \
129 (DT_INST_PROP(n, clk32k_ch2_enable) << 2U) | \
130 (DT_INST_PROP(n, clk32k_ch3_enable) << 3U) | \
131 (DT_INST_PROP(n, clk32k_ch4_enable) << 4U) | \
132 (DT_INST_PROP(n, clk32k_ch5_enable) << 5U)), \
133 }; \
134 \
135 DEVICE_DT_INST_DEFINE(n, pwm_b91_init, \
136 NULL, NULL, &config##n, \
137 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
138 &pwm_b91_driver_api);
139
140 DT_INST_FOREACH_STATUS_OKAY(PWM_B91_INIT)
141
