1 /* 2 * Copyright (c) 2017 - 2025, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, this 11 * list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived from this 19 * software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef NRFX_PRS_H__ 35 #define NRFX_PRS_H__ 36 37 #include <nrfx.h> 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /** 44 * @defgroup nrfx_prs Peripheral Resource Sharing (PRS) 45 * @{ 46 * @ingroup nrfx 47 * 48 * @brief Peripheral Resource Sharing interface (PRS). 49 */ 50 51 #if defined(NRF51) 52 // SPI0, TWI0 53 #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 54 // SPI1, SPIS1, TWI1 55 #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 56 #elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA) 57 // TWIM0, TWIS0, TWI0 58 #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 59 // SPIM0, SPIS0, SPI0 60 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 61 // UARTE0, UART0 62 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 63 #elif defined(NRF52811_XXAA) 64 // TWIM0, TWIS0, TWI0, SPIM1, SPIS1, SPI1 65 #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 66 // SPIM0, SPIS0, SPI0 67 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 68 // UART0, UARTE0 69 #define NRFX_PRS_BOX_2_ADDR NRF_UART0 70 #elif defined(NRF52820_XXAA) 71 // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 72 #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 73 // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 74 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 75 // UARTE0, UART0 76 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 77 #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ 78 defined(NRF52833_XXAA) || defined(NRF52840_XXAA) 79 // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 80 #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 81 // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 82 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 83 // SPIM2, SPIS2, SPI2 84 #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 85 // COMP, LPCOMP 86 #define NRFX_PRS_BOX_3_ADDR NRF_COMP 87 // UARTE0, UART0 88 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 89 #elif defined(NRF5340_XXAA_APPLICATION) 90 // SPIM0, SPIS0, TWIM0, TWIS0, UARTE0 91 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 92 // SPIM1, SPIS1, TWIM1, TWIS1, UARTE1 93 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE1 94 // SPIM2, SPIS2, TWIM2, TWIS2, UARTE2 95 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2 96 // SPIM3, SPIS3, TWIM3, TWIS3, UARTE3 97 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3 98 // COMP, LPCOMP 99 #define NRFX_PRS_BOX_4_ADDR NRF_COMP 100 #elif defined(NRF5340_XXAA_NETWORK) 101 // SPIM0, SPIS0, TWIM0, TWIS0, UARTE0 102 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 103 #elif defined(NRF54H20_XXAA) 104 // SPIM130, SPIS130, TWIM130, TWIS130, UARTE130 105 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE130 106 // SPIM131, SPIS131, TWIM131, TWIS131, UARTE131 107 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE131 108 // SPIM132, SPIS132, TWIM132, TWIS132, UARTE132 109 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE132 110 // SPIM133, SPIS133, TWIM133, TWIS133, UARTE133 111 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE133 112 // SPIM134, SPIS134, TWIM134, TWIS134, UARTE134 113 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE134 114 // SPIM135, SPIS135, TWIM135, TWIS135, UARTE135 115 #define NRFX_PRS_BOX_5_ADDR NRF_UARTE135 116 // SPIM136, SPIS136, TWIM136, TWIS136, UARTE136 117 #define NRFX_PRS_BOX_6_ADDR NRF_UARTE136 118 // SPIM137, SPIS137, TWIM137, TWIS137, UARTE137 119 #define NRFX_PRS_BOX_7_ADDR NRF_UARTE137 120 // SPIM120, UARTE120 121 #define NRFX_PRS_BOX_8_ADDR NRF_UARTE120 122 // COMP, LPCOMP 123 #define NRFX_PRS_BOX_9_ADDR NRF_COMP 124 #elif defined(NRF54L09_ENGA_XXAA) 125 // SPIM20, SPIS20, TWIM20, TWIS20, UARTE20 126 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE20 127 // SPIM21, SPIS21, TWIM21, TWIS21, UARTE21 128 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE21 129 // SPIM30, SPIS30, TWIM30, TWIS30, UARTE30 130 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE30 131 // COMP, LPCOMP 132 #define NRFX_PRS_BOX_3_ADDR NRF_COMP 133 #elif defined(NRF54L05_XXAA) || defined(NRF54L10_XXAA) || defined(NRF54L15_XXAA) 134 // SPIM00, SPIS00, UARTE00 135 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE00 136 // SPIM20, SPIS20, TWIM20, TWIS20, UARTE20 137 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE20 138 // SPIM21, SPIS21, TWIM21, TWIS21, UARTE21 139 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE21 140 // SPIM22, SPIS22, TWIM22, TWIS22, UARTE22 141 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE22 142 // SPIM30, SPIS30, TWIM30, TWIS30, UARTE30 143 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE30 144 // COMP, LPCOMP 145 #define NRFX_PRS_BOX_5_ADDR NRF_COMP 146 #elif defined(NRF54L20_ENGA_XXAA) 147 // SPIM00, SPIS00, UARTE00 148 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE00 149 // SPIM20, SPIS20, TWIM20, TWIS20, UARTE20 150 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE20 151 // SPIM21, SPIS21, TWIM21, TWIS21, UARTE21 152 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE21 153 // SPIM22, SPIS22, TWIM22, TWIS22, UARTE22 154 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE22 155 // SPIM23, SPIS23, TWIM23, TWIS23, UARTE23 156 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE23 157 // SPIM24, SPIS24, TWIM24, TWIS24, UARTE23 158 #define NRFX_PRS_BOX_5_ADDR NRF_UARTE24 159 // SPIM30, SPIS30, TWIM30, TWIS30, UARTE30 160 #define NRFX_PRS_BOX_6_ADDR NRF_UARTE30 161 // COMP, LPCOMP 162 #define NRFX_PRS_BOX_7_ADDR NRF_COMP 163 #elif defined(NRF7120_ENGA_XXAA) 164 // SPIM00, UARTE00 165 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE00 166 // SPIM01 167 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM01 168 // SPIM02 169 #define NRFX_PRS_BOX_2_ADDR NRF_SPIM02 170 // SPIM20, SPIS20, TWIM20, TWIS20, UARTE20 171 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE20 172 // SPIM21, SPIS21, TWIM21, TWIS21, UARTE21 173 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE21 174 // SPIM22, SPIS22, TWIM22, TWIS22, UARTE22 175 #define NRFX_PRS_BOX_5_ADDR NRF_UARTE22 176 // SPIM23, SPIS23, TWIM23, TWIS23, UARTE23 177 #define NRFX_PRS_BOX_6_ADDR NRF_UARTE23 178 // SPIM24, SPIS24, TWIM24, TWIS24, UARTE24 179 #define NRFX_PRS_BOX_7_ADDR NRF_UARTE24 180 // SPIM30, SPIS30, TWIM30, TWIS30, UARTE30 181 #define NRFX_PRS_BOX_8_ADDR NRF_UARTE30 182 // COMP, LPCOMP 183 #define NRFX_PRS_BOX_9_ADDR NRF_COMP 184 #elif defined(NRF91_SERIES) 185 // UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 186 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 187 // UARTE1, SPIM1, SPIS1, TWIM1, TWIS1 188 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE1 189 // UARTE2, SPIM2, SPIS2, TWIM2, TWIS2 190 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2 191 // UARTE3, SPIM3, SPIS3, TWIM3, TWIS3 192 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3 193 #elif defined(NRF9230_ENGB_XXAA) 194 // SPIM130, SPIS130, TWIM130, TWIS130, UARTE130 195 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE130 196 // SPIM131, SPIS131, TWIM131, TWIS131, UARTE131 197 #define NRFX_PRS_BOX_1_ADDR NRF_UARTE131 198 // SPIM132, SPIS132, TWIM132, TWIS132, UARTE132 199 #define NRFX_PRS_BOX_2_ADDR NRF_UARTE132 200 // SPIM133, SPIS133, TWIM133, TWIS133, UARTE133 201 #define NRFX_PRS_BOX_3_ADDR NRF_UARTE133 202 // SPIM134, SPIS134, TWIM134, TWIS134, UARTE134 203 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE134 204 // SPIM135, SPIS135, TWIM135, TWIS135, UARTE135 205 #define NRFX_PRS_BOX_5_ADDR NRF_UARTE135 206 // SPIM136, SPIS136, TWIM136, TWIS136, UARTE136 207 #define NRFX_PRS_BOX_6_ADDR NRF_UARTE136 208 // SPIM137, SPIS137, TWIM137, TWIS137, UARTE137 209 #define NRFX_PRS_BOX_7_ADDR NRF_UARTE137 210 // SPIS120, UARTE120 211 #define NRFX_PRS_BOX_8_ADDR NRF_UARTE120 212 // COMP, LPCOMP 213 #define NRFX_PRS_BOX_9_ADDR NRF_COMP 214 #elif !defined(NRF_PRS_BOX_EXT) 215 #error "Unknown device." 216 #endif 217 218 /** 219 * @brief Function for acquiring shared peripheral resources associated with 220 * the specified peripheral. 221 * 222 * Certain resources and registers are shared among peripherals that have 223 * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0 in 224 * nRF52832). Only one of them can be utilized at a given time. This function 225 * reserves proper resources to be used by the specified peripheral. 226 * If NRFX_PRS_ENABLED is set to a non-zero value, IRQ handlers for peripherals 227 * that are sharing resources with others are implemented by the @ref nrfx_prs 228 * module instead of individual drivers. The drivers must then specify their 229 * interrupt handling routines and register them by using this function. 230 * 231 * @param[in] p_base_addr Requested peripheral base pointer. 232 * @param[in] irq_handler Interrupt handler to register. 233 * 234 * @retval NRFX_SUCCESS If resources were acquired successfully or the 235 * specified peripheral is not handled by the PRS 236 * subsystem and there is no need to acquire resources 237 * for it. 238 * @retval NRFX_ERROR_BUSY If resources were already acquired. 239 */ 240 nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, 241 nrfx_irq_handler_t irq_handler); 242 243 /** 244 * @brief Function for releasing shared resources reserved previously by 245 * @ref nrfx_prs_acquire() for the specified peripheral. 246 * 247 * @param[in] p_base_addr Released peripheral base pointer. 248 */ 249 void nrfx_prs_release(void const * p_base_addr); 250 251 /** @} */ 252 253 /* 254 * Declare interrupt handlers for all enabled driver instances in the following format: 255 * nrfx_\<periph_name\>_\<idx\>_irq_handler (for example, nrfx_prs_box_0_irq_handler). 256 * 257 * A specific interrupt handler for the driver instance can be retrieved by using 258 * the NRFX_PRS_BOX_INST_HANDLER_GET macro. 259 * 260 * Here is a sample of using the NRFX_PRS_BOX_INST_HANDLER_GET macro to map an interrupt handler 261 * in a Zephyr application: 262 * 263 * IRQ_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_PRS_BOX_INST_GET(\<instance_index\>)), \<priority\>, 264 * NRFX_PRS_BOX_INST_HANDLER_GET(\<instance_index\>), 0, 0); 265 */ 266 NRFX_INSTANCE_IRQ_HANDLERS_DECLARE(PRS_BOX_, prs_box) 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 #endif // NRFX_PRS_H__ 273
