1 /***************************************************************************//**
2 * @file
3 * @brief This file contains the type definitions for efr32xg2x chip specific
4 * aspects of RAIL.
5 *******************************************************************************
6 * # License
7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
8 *******************************************************************************
9 *
10 * SPDX-License-Identifier: Zlib
11 *
12 * The licensor of this software is Silicon Laboratories Inc.
13 *
14 * This software is provided 'as-is', without any express or implied
15 * warranty. In no event will the authors be held liable for any damages
16 * arising from the use of this software.
17 *
18 * Permission is granted to anyone to use this software for any purpose,
19 * including commercial applications, and to alter it and redistribute it
20 * freely, subject to the following restrictions:
21 *
22 * 1. The origin of this software must not be misrepresented; you must not
23 * claim that you wrote the original software. If you use this software
24 * in a product, an acknowledgment in the product documentation would be
25 * appreciated but is not required.
26 * 2. Altered source versions must be plainly marked as such, and must not be
27 * misrepresented as being the original software.
28 * 3. This notice may not be removed or altered from any source distribution.
29 *
30 ******************************************************************************/
31
32 #ifndef __RAIL_CHIP_SPECIFIC_H_
33 #if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS)
34 #warning rail_chip_specific.h should only be included by rail_types.h
35 #include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h
36 #else // __RAIL_TYPES_H__
37 /// Include guard
38 #define __RAIL_CHIP_SPECIFIC_H_
39
40 #include "rail_features.h"
41 #ifdef RAIL_INTERNAL_BUILD
42 #include "rail_chip_specific_internal.h"
43 #endif
44
45 #if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM))
46 // Copied from rail_types.h to satisfy doxygen build.
47 /// The RAIL library does not use enumerations because the ARM EABI leaves their
48 /// size ambiguous, which causes problems if the application is built
49 /// with different flags than the library. Instead, uint8_t typedefs
50 /// are used in compiled code for all enumerations. For documentation purposes, this is
51 /// converted to an actual enumeration since it's much easier to read in Doxygen.
52 #define RAIL_ENUM(name) enum name
53 /// This macro is a more generic version of the \ref RAIL_ENUM() macro that
54 /// allows the size of the type to be overridden instead of forcing the use of
55 /// a uint8_t. See \ref RAIL_ENUM() for more information.
56 #define RAIL_ENUM_GENERIC(name, type) enum name
57 #endif//(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM))
58
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62
63 /**
64 * @addtogroup General_EFR32XG2 EFR32xG2
65 * @{
66 * @brief EFR32xG2-specific initialization data types
67 * @ingroup General
68 */
69
70 /**
71 * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle is
72 * not recommended. As a result, another value that can't be de-referenced is used.
73 *
74 * This generic handle can and should be used for RAIL APIs that are called
75 * prior to RAIL initialization.
76 */
77 #define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL)
78
79 #ifndef DOXYGEN_SHOULD_SKIP_THIS
80
81 /**
82 * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES
83 * @brief The EFR32XG21 series size needed for
84 * \ref RAIL_StateBufferEntry_t::bufferBytes.
85 */
86 #define RAIL_EFR32XG21_STATE_BUFFER_BYTES 528
87
88 /**
89 * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES
90 * @brief The EFR32XG22 series size needed for
91 * \ref RAIL_StateBufferEntry_t::bufferBytes.
92 */
93 #define RAIL_EFR32XG22_STATE_BUFFER_BYTES 568
94
95 /**
96 * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES
97 * @brief The EFR32XG23 series size needed for
98 * \ref RAIL_StateBufferEntry_t::bufferBytes.
99 */
100 #define RAIL_EFR32XG23_STATE_BUFFER_BYTES 568
101
102 /**
103 * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES
104 * @brief The EFR32XG24 series size needed for
105 * \ref RAIL_StateBufferEntry_t::bufferBytes.
106 */
107 #define RAIL_EFR32XG24_STATE_BUFFER_BYTES 584
108
109 /**
110 * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES
111 * @brief The EFR32XG25 series size needed for
112 * \ref RAIL_StateBufferEntry_t::bufferBytes.
113 */
114 #define RAIL_EFR32XG25_STATE_BUFFER_BYTES 608
115
116 /**
117 * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES
118 * @brief The EFR32XG27 series size needed for
119 * \ref RAIL_StateBufferEntry_t::bufferBytes.
120 */
121 #define RAIL_EFR32XG27_STATE_BUFFER_BYTES 568
122
123 /**
124 * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES
125 * @brief The EFR32XG28 series size needed for
126 * \ref RAIL_StateBufferEntry_t::bufferBytes.
127 */
128 #define RAIL_EFR32XG28_STATE_BUFFER_BYTES 568
129
130 #ifndef RAIL_STATE_BUFFER_BYTES
131 /**
132 * @def RAIL_STATE_BUFFER_BYTES
133 * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes
134 * on this platform for this radio. This compile-time size may be slightly
135 * larger than what \ref RAIL_GetStateBufferSize() determines at run-time.
136 */
137 #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
138 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES
139 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
140 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES
141 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
142 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES
143 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
144 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES
145 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
146 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES
147 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)
148 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES
149 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
150 #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES
151 #else
152 #define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen
153 #error "Unsupported platform!"
154 #endif
155 #endif //#ifndef RAIL_STATE_BUFFER_BYTES
156 #endif//DOXYGEN_SHOULD_SKIP_THIS
157
158 /**
159 * @struct RAILSched_Config_t
160 * @brief Provided for backwards compatibility.
161 */
162 typedef struct RAILSched_Config {
163 uint8_t buffer[1]; /**< Dummy buffer no longer used. */
164 } RAILSched_Config_t;
165
166 /**
167 * @typedef RAIL_StateBuffer_t
168 * @brief Provided for backwards compatibility.
169 */
170 typedef uint8_t RAIL_StateBuffer_t[1];
171
172 /**
173 * @struct RAIL_Config_t
174 * @brief RAIL configuration structure.
175 */
176 typedef struct RAIL_Config {
177 /**
178 * A pointer to a function, which is called whenever a RAIL event occurs.
179 *
180 * @param[in] railHandle A handle for a RAIL instance.
181 * @param[in] events A bit mask of RAIL events.
182 *
183 * See the \ref RAIL_Events_t documentation for the list of RAIL events.
184 */
185 void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events);
186 /**
187 * Provided for backwards compatibility. Ignored.
188 */
189 void *protocol;
190 /**
191 * Provided for backwards compatibility. Ignored.
192 */
193 RAILSched_Config_t *scheduler;
194 /**
195 * Provided for backwards compatibility. Ignored.
196 */
197 RAIL_StateBuffer_t buffer;
198 } RAIL_Config_t;
199
200 #ifndef DOXYGEN_SHOULD_SKIP_THIS
201 /**
202 * @enum RAIL_RadioStateEfr32_t
203 * @brief Radio state machine statuses.
204 */
RAIL_ENUM(RAIL_RadioStateEfr32_t)205 RAIL_ENUM(RAIL_RadioStateEfr32_t) {
206 RAIL_RAC_STATE_OFF, /**< Radio is off. */
207 RAIL_RAC_STATE_RXWARM, /**< Radio is enabling the receiver. */
208 RAIL_RAC_STATE_RXSEARCH, /**< Radio is listening for incoming frames. */
209 RAIL_RAC_STATE_RXFRAME, /**< Radio is receiving a frame. */
210 RAIL_RAC_STATE_RXPD, /**< Radio is powering down receiver and going to
211 OFF state. */
212 RAIL_RAC_STATE_RX2RX, /**< Radio is going back to receive mode after
213 receiving a frame. */
214 RAIL_RAC_STATE_RXOVERFLOW, /**< Received data was lost due to full receive
215 buffer. */
216 RAIL_RAC_STATE_RX2TX, /**< Radio is disabling receiver and enabling
217 transmitter. */
218 RAIL_RAC_STATE_TXWARM, /**< Radio is enabling transmitter. */
219 RAIL_RAC_STATE_TX, /**< Radio is transmitting data. */
220 RAIL_RAC_STATE_TXPD, /**< Radio is powering down transmitter and going
221 to OFF state. */
222 RAIL_RAC_STATE_TX2RX, /**< Radio is disabling transmitter and enabling
223 reception. */
224 RAIL_RAC_STATE_TX2TX, /**< Radio is preparing a transmission after the
225 previous transmission was ended. */
226 RAIL_RAC_STATE_SHUTDOWN, /**< Radio is powering down receiver and going to
227 OFF state. */
228 #if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
229 RAIL_RAC_STATE_POR, /**< Radio power-on-reset state. */
230 #endif
231 RAIL_RAC_STATE_NONE /**< Invalid Radio state, must be the last entry */
232 };
233
234 // Self-referencing defines minimize compiler complaints when using RAIL_ENUM
235 #define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF)
236 #define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM)
237 #define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH)
238 #define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME)
239 #define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD)
240 #define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX)
241 #define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW)
242 #define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX)
243 #define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM)
244 #define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX)
245 #define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD)
246 #define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX)
247 #define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX)
248 #define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN)
249 #if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
250 #define RAIL_RAC_STATE_POR ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_POR)
251 #endif
252 #define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE)
253 #endif//DOXYGEN_SHOULD_SKIP_THIS
254
255 #ifndef DOXYGEN_SHOULD_SKIP_THIS
256 /**
257 * @struct RAIL_RffpllConfig_t
258 * @brief Stores information relevant to the Radio-Friendly Frequency
259 * Phase-Locked Loop (RFFPLL) for the PHY configuration currently loaded in
260 * memory.
261 */
262 typedef struct {
263 uint32_t dividers; // Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values
264 uint32_t radioFreqHz; // Radio clock frequency in Hz
265 uint32_t sysclkFreqHz; // System clock frequency in Hz
266 } RAIL_RffpllConfig_t;
267
268 /**
269 * @def RAIL_RFFPLL_DIVIDERX_MASK
270 * @brief Bit mask for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers.
271 */
272 #define RAIL_RFFPLL_DIVIDERX_MASK 0x000000FFUL
273
274 /**
275 * @def RAIL_RFFPLL_DIVIDERX_SHIFT
276 * @brief Shift value for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers.
277 */
278 #define RAIL_RFFPLL_DIVIDERX_SHIFT 0
279
280 /**
281 * @def RAIL_RFFPLL_DIVIDERY_MASK
282 * @brief Bit mask for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers.
283 */
284 #define RAIL_RFFPLL_DIVIDERY_MASK 0x0000FF00UL
285
286 /**
287 * @def RAIL_RFFPLL_DIVIDERY_SHIFT
288 * @brief Shift value for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers.
289 */
290 #define RAIL_RFFPLL_DIVIDERY_SHIFT 8
291
292 /**
293 * @def RAIL_RFFPLL_DIVIDERN_MASK
294 * @brief Bit mask for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers.
295 */
296 #define RAIL_RFFPLL_DIVIDERN_MASK 0x00FF0000UL
297
298 /**
299 * @def RAIL_RFFPLL_DIVIDERN_SHIFT
300 * @brief Shift value for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers.
301 */
302 #define RAIL_RFFPLL_DIVIDERN_SHIFT 16
303 #endif//DOXYGEN_SHOULD_SKIP_THIS
304 /** @} */ // end of group General_EFR32XG2
305
306 // -----------------------------------------------------------------------------
307 // Multiprotocol
308 // -----------------------------------------------------------------------------
309 /**
310 * @addtogroup Multiprotocol_EFR32 EFR32
311 * @{
312 * @brief EFR32-specific multiprotocol support defines
313 * @ingroup Multiprotocol
314 */
315
316 /**
317 * @def TRANSITION_TIME_US
318 * @brief Time it takes to take care of protocol switching.
319 */
320 #if _SILICON_LABS_32B_SERIES_2_CONFIG > 1
321 // XG22 + devices
322 #define TRANSITION_TIME_US 510
323 #else
324 // XG21
325 #define TRANSITION_TIME_US 500
326 #endif
327
328 /** @} */ // end of group Multiprotocol_EFR32
329
330 // -----------------------------------------------------------------------------
331 // Antenna Control
332 // -----------------------------------------------------------------------------
333 /**
334 * @addtogroup Antenna_Control_EFR32XG2X EFR32XG2X
335 * @{
336 * @brief EFR32 Antenna Control Functionality
337 * @ingroup Antenna_Control
338 *
339 * These enumerations and structures are used with RAIL Antenna Control API. EFR32 supports
340 * up to two antennas with configurable pin locations.
341 */
342
343 /** Antenna path Selection enumeration. */
RAIL_ENUM(RAIL_AntennaSel_t)344 RAIL_ENUM(RAIL_AntennaSel_t) {
345 /** Enum for antenna path 0. */
346 RAIL_ANTENNA_0 = 0,
347 /** Enum for antenna path 1. */
348 RAIL_ANTENNA_1 = 1,
349 /** Enum for antenna path auto. */
350 RAIL_ANTENNA_AUTO = 255,
351 };
352
353 #ifndef DOXYGEN_SHOULD_SKIP_THIS
354 // Self-referencing defines minimize compiler complaints when using RAIL_ENUM
355 #define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0)
356 #define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1)
357 #define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO)
358 #endif//DOXYGEN_SHOULD_SKIP_THIS
359
360 /**
361 * @struct RAIL_AntennaConfig_t
362 * @brief A configuration for antenna selection.
363 */
364 typedef struct RAIL_AntennaConfig {
365 /** Antenna 0 Pin Enable */
366 bool ant0PinEn;
367 /** Antenna 1 Pin Enable */
368 bool ant1PinEn;
369 /** Internal default RF path (EFR32 series 2);
370 * defaultPath is ignored on EFR32 series 2 parts that have only
371 * one RF path bonded out and on EFR32xG27 dual-band OPNs where
372 * the appropriate RF path is automatically set by RAIL to
373 * 0 for 2.4GHZ band and 1 for SubGHz band PHYs. */
374 RAIL_AntennaSel_t defaultPath;
375 /** Antenna 0 output GPIO port */
376 uint8_t ant0Port;
377 /** Antenna 0 output GPIO pin */
378 uint8_t ant0Pin;
379 /** Reserved */
380 uint8_t reserved;
381 /** Antenna 1 output GPIO port */
382 uint8_t ant1Port;
383 /** Antenna 1 output GPIO pin */
384 uint8_t ant1Pin;
385 } RAIL_AntennaConfig_t;
386
387 /** @} */ // end of group Antenna_Control_EFR32
388
389 // -----------------------------------------------------------------------------
390 // Calibration
391 // -----------------------------------------------------------------------------
392 /**
393 * @addtogroup Calibration_EFR32XG2X EFR32XG2X
394 * @{
395 * @brief EFR32XG2X-specific Calibrations
396 * @ingroup Calibration
397 *
398 * The EFR32 supports the Image Rejection (IR)
399 * calibration and a temperature-dependent calibration. The IR calibration
400 * can be computed once and stored off or computed each time at
401 * startup. Because it is PHY-specific and provides sensitivity improvements,
402 * it is highly recommended. The IR calibration should only be run when the
403 * radio is IDLE.
404 *
405 * The temperature-dependent calibrations are used to recalibrate the synth if
406 * the temperature crosses 0C or the temperature delta since the last
407 * calibration exceeds 70C while in receive. RAIL will run the VCO calibration
408 * automatically upon entering receive or transmit states, so the application
409 * can omit this calibration if the stack re-enters receive or transmit with
410 * enough frequency to avoid reaching the temperature delta. If the application
411 * does not calibrate for temperature, it's possible to miss receive packets due
412 * to a drift in the carrier frequency.
413 */
414
415 /** EFR32-specific temperature calibration bit */
416 #define RAIL_CAL_TEMP_VCO (0x00000001U)
417
418 #if RAIL_SUPPORTS_HFXO_COMPENSATION
419 /** EFR32-specific HFXO temperature check bit */
420 #define RAIL_CAL_TEMP_HFXO (0x00000002U)
421 /** EFR32-specific HFXO compensation bit */
422 #define RAIL_CAL_COMPENSATE_HFXO (0x00000004U)
423 #else
424 /** EFR32-specific HFXO temperature check bit */
425 #define RAIL_CAL_TEMP_HFXO (0U)
426 /** EFR32-specific HFXO compensation bit */
427 #define RAIL_CAL_COMPENSATE_HFXO (0U)
428 #endif
429
430 /** EFR32-specific IR calibration bit */
431 #define RAIL_CAL_RX_IRCAL (0x00010000U)
432
433 #if RAIL_SUPPORTS_OFDM_PA
434 /** EFR32-specific Tx IR calibration bit */
435 #define RAIL_CAL_OFDM_TX_IRCAL (0x00100000U)
436 #else
437 /** EFR32-specific Tx IR calibration bit */
438 #define RAIL_CAL_OFDM_TX_IRCAL (0U)
439 #endif
440
441 /** EFR32-specific IR calibration bit */
442 #define RAIL_CAL_ONETIME_IRCAL (RAIL_CAL_RX_IRCAL | RAIL_CAL_OFDM_TX_IRCAL)
443
444 /** A mask to run temperature-dependent calibrations */
445 #define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO | RAIL_CAL_TEMP_HFXO | RAIL_CAL_COMPENSATE_HFXO)
446 /** A mask to run one-time calibrations */
447 #define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL)
448 /** A mask to run optional performance calibrations */
449 #define RAIL_CAL_PERF (0)
450 /** A mask for calibrations that require the radio to be off */
451 #define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL)
452 /** A mask to run all possible calibrations for this chip */
453 #define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME)
454 /** A mask to run all pending calibrations */
455 #define RAIL_CAL_ALL_PENDING (0x00000000U)
456 /** An invalid calibration value */
457 #define RAIL_CAL_INVALID_VALUE (0xFFFFFFFFU)
458
459 /**
460 * @def RAIL_RF_PATHS_2P4GIG
461 * @brief Indicates the number of 2.4 GHz RF Paths suppported
462 */
463 #ifndef RAIL_RF_PATHS_2P4GIG
464 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 || _SILICON_LABS_32B_SERIES_2_CONFIG == 4
465 #define RAIL_RF_PATHS_2P4GIG 2
466 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
467 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \
468 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
469 #define RAIL_RF_PATHS_2P4GIG 1
470 #else
471 #define RAIL_RF_PATHS_2P4GIG 0
472 #endif
473
474 /**
475 * @def RAIL_RF_PATHS_SUBGIG
476 * @brief Indicates the number of sub-GHz RF Paths supported
477 */
478 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3
479 #define RAIL_RF_PATHS_SUBGIG 2
480 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5
481 #define RAIL_RF_PATHS_SUBGIG 2
482 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8
483 #define RAIL_RF_PATHS_SUBGIG 1
484 #else
485 #define RAIL_RF_PATHS_SUBGIG 0
486 #endif
487 #endif //#ifndef RAIL_RF_PATHS_2P4GIG
488
489 /**
490 * @def RAIL_RF_PATHS
491 * @brief Indicates the number of RF Paths supported
492 */
493 #define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG)
494
495 /**
496 * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
497 * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths
498 * Needed for backwards compatibility.
499 */
500 #if RAIL_RF_PATHS > 1
501 #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1
502 #else
503 #ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen
504 #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0
505 #endif//DOXYGEN_SHOULD_SKIP_THIS
506 #endif
507
508 #if RAIL_SUPPORTS_OFDM_PA
509 /**
510 * @typedef RAIL_TxIrCalValues_t
511 * @brief A Tx IR calibration value structure.
512 *
513 * This definition contains the set of persistent calibration values for
514 * OFDM on EFR32. You can set these beforehand and apply them at startup to save the
515 * time required to compute them. Any of these values may be set to
516 * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
517 */
518 typedef struct RAIL_TxIrCalValues {
519 uint32_t dcOffsetIQ; // TXIRCAL result
520 uint32_t phiEpsilon; // TXIRCAL result
521 } RAIL_TxIrCalValues_t;
522
523 /**
524 * A define to set all RAIL_TxIrCalValues_t values to uninitialized.
525 *
526 * This define can be used when you have no data to pass to the calibration
527 * routines but wish to compute and save all possible calibrations.
528 */
529 #define RAIL_IRCALVALUES_TX_UNINIT { \
530 RAIL_CAL_INVALID_VALUE, \
531 RAIL_CAL_INVALID_VALUE, \
532 }
533
534 /**
535 * @typedef RAIL_IrCalValues_t
536 * @brief An IR calibration value structure.
537 *
538 * This definition contains the set of persistent calibration values for
539 * EFR32. You can set these beforehand and apply them at startup to save the
540 * time required to compute them. Any of these values may be set to
541 * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
542 */
543 typedef struct RAIL_IrCalValues {
544 uint32_t rxIrCalValues[RAIL_RF_PATHS]; /**< An Image Rejection (IR) calibration value */
545 RAIL_TxIrCalValues_t txIrCalValues; /**< An Image Rejection (IR) calibration value for OFDM Tx*/
546 } RAIL_IrCalValues_t;
547
548 /**
549 * A define allowing Rx calibration value access compatibility
550 * between series 1 and series 2.
551 */
552 #define RAIL_IRCALVAL(irCalStruct, rfPath) \
553 ((irCalStruct).rxIrCalValues[(rfPath)])
554
555 /**
556 * A define to set all RAIL_IrCalValues_t values to uninitialized.
557 *
558 * This define can be used when you have no data to pass to the calibration
559 * routines but wish to compute and save all possible calibrations.
560 */
561 #if (RAIL_RF_PATHS == 2)
562 #define RAIL_IRCALVALUES_UNINIT { \
563 { RAIL_CAL_INVALID_VALUE, RAIL_CAL_INVALID_VALUE }, \
564 RAIL_IRCALVALUES_TX_UNINIT, \
565 }
566 #elif (RAIL_RF_PATHS == 1)
567 #define RAIL_IRCALVALUES_UNINIT { \
568 { RAIL_CAL_INVALID_VALUE }, \
569 RAIL_IRCALVALUES_TX_UNINIT, \
570 }
571 #else
572 #error "This config is not valid, RAIL_RF_PATHS has to be either 1 or 2"
573 #endif
574
575 #else // RAIL_SUPPORTS_OFDM_PA
576 /**
577 * @typedef RAIL_IrCalValues_t
578 * @brief An IR calibration value structure.
579 *
580 * This definition contains the set of persistent calibration values for
581 * EFR32. You can set these beforehand and apply them at startup to save the
582 * time required to compute them. Any of these values may be set to
583 * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
584 */
585 typedef uint32_t RAIL_IrCalValues_t[RAIL_RF_PATHS];
586
587 /**
588 * A define allowing Rx calibration value access compatibility
589 * between series 1 and series 2.
590 */
591 #define RAIL_IRCALVAL(irCalStruct, rfPath) \
592 ((irCalStruct)[(rfPath)])
593
594 /**
595 * A define to set all RAIL_IrCalValues_t values to uninitialized.
596 *
597 * This define can be used when you have no data to pass to the calibration
598 * routines but wish to compute and save all possible calibrations.
599 */
600 #if (RAIL_RF_PATHS == 2)
601 #define RAIL_IRCALVALUES_UNINIT { \
602 RAIL_CAL_INVALID_VALUE, \
603 RAIL_CAL_INVALID_VALUE, \
604 }
605 #elif (RAIL_RF_PATHS == 1)
606 #define RAIL_IRCALVALUES_UNINIT { \
607 RAIL_CAL_INVALID_VALUE, \
608 }
609 #else
610 #error "This config is not valid, RAIL_RF_PATHS has to be either 1 or 2"
611 #endif
612
613 #endif // RAIL_SUPPORTS_OFDM_PA
614
615 /**
616 * @struct RAIL_ChannelConfigEntryAttr
617 * @brief A channel configuration entry attribute structure. Items listed
618 * are designed to be altered and updated during run-time.
619 */
620 struct RAIL_ChannelConfigEntryAttr {
621 RAIL_IrCalValues_t calValues; /**< IR calibration attributes specific to
622 each channel configuration entry. */
623 };
624
625 /**
626 * Applies a given image rejection calibration value.
627 *
628 * @param[in] railHandle A RAIL instance handle.
629 * @param[in] imageRejection The image rejection value to apply.
630 * @return A status code indicating success of the function call.
631 *
632 * Take an image rejection calibration value and apply it. This value should be
633 * determined from a previous run of \ref RAIL_CalibrateIr on the same
634 * physical device with the same radio configuration. The imageRejection value
635 * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible.
636 *
637 * If multiple protocols are used, this function will return
638 * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
639 * not active. In that case, the caller must attempt to re-call this function later.
640 *
641 * @deprecated Please use \ref RAIL_ApplyIrCalibrationAlt instead.
642 */
643 RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle,
644 uint32_t imageRejection);
645
646 /**
647 * Applies a given image rejection calibration value.
648 *
649 * @param[in] railHandle A RAIL instance handle.
650 * @param[in] imageRejection Pointer to the image rejection value to apply.
651 * @param[in] rfPath RF path to calibrate.
652 * @return A status code indicating success of the function call.
653 *
654 * Take an image rejection calibration value and apply it. This value should be
655 * determined from a previous run of \ref RAIL_CalibrateIrAlt on the same
656 * physical device with the same radio configuration. The imageRejection value
657 * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible.
658 * @note: To make sure the imageRejection value is stored/configured correctly,
659 * \ref RAIL_ConfigAntenna should be called before calling this API.
660 *
661 * If multiple protocols are used, this function will return
662 * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
663 * not active. In that case, the caller must attempt to re-call this function later.
664 */
665 RAIL_Status_t RAIL_ApplyIrCalibrationAlt(RAIL_Handle_t railHandle,
666 RAIL_IrCalValues_t *imageRejection,
667 RAIL_AntennaSel_t rfPath);
668
669 /**
670 * Runs the image rejection calibration.
671 *
672 * @param[in] railHandle A RAIL instance handle.
673 * @param[out] imageRejection The result of the image rejection calibration.
674 * @return A status code indicating success of the function call.
675 *
676 * Run the image rejection calibration and apply the resulting value. If the
677 * imageRejection parameter is not NULL, store the value at that
678 * location. The imageRejection value will also be stored to the
679 * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running
680 * calibration that adds significant code space when run and can be run with a
681 * separate firmware image on each device to save code space in the
682 * final image.
683 *
684 * If multiple protocols are used, this function will return
685 * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
686 * not active. In that case, the caller must attempt to re-call this function later.
687 *
688 * @deprecated Please use \ref RAIL_CalibrateIrAlt instead.
689 */
690 RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle,
691 uint32_t *imageRejection);
692
693 /**
694 * Runs the image rejection calibration.
695 *
696 * @param[in] railHandle A RAIL instance handle.
697 * @param[out] imageRejection Pointer to the image rejection result.
698 * @param[in] rfPath RF path to calibrate.
699 * @return A status code indicating success of the function call.
700 *
701 * Run the image rejection calibration and apply the resulting value. If the
702 * imageRejection parameter is not NULL, store the value at that
703 * location. The imageRejection value will also be stored to the
704 * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running
705 * calibration that adds significant code space when run and can be run with a
706 * separate firmware image on each device to save code space in the
707 * final image.
708 * @note: To make sure the imageRejection value is stored/configured correctly,
709 * \ref RAIL_ConfigAntenna should be called before calling this API.
710 *
711 * If multiple protocols are used, this function will return
712 * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
713 * not active. In that case, the caller must attempt to re-call this function later.
714 */
715 RAIL_Status_t RAIL_CalibrateIrAlt(RAIL_Handle_t railHandle,
716 RAIL_IrCalValues_t *imageRejection,
717 RAIL_AntennaSel_t rfPath);
718
719 /**
720 * Calibrates image rejection for IEEE 802.15.4 2.4 GHz
721 *
722 * @param[in] railHandle A RAIL instance handle.
723 * @param[out] imageRejection The result of the image rejection calibration.
724 * @return A status code indicating success of the function call.
725 *
726 * Some chips have protocol-specific image rejection calibrations programmed
727 * into their flash. This function will either get the value from flash and
728 * apply it, or run the image rejection algorithm to find the value.
729 */
730 RAIL_Status_t RAIL_IEEE802154_CalibrateIr2p4Ghz(RAIL_Handle_t railHandle,
731 uint32_t *imageRejection);
732
733 /**
734 * Calibrates image rejection for IEEE 802.15.4 915 MHz and 868 MHz
735 *
736 * @param[in] railHandle A RAIL instance handle.
737 * @param[out] imageRejection The result of the image rejection calibration.
738 * @return A status code indicating success of the function call.
739 *
740 * Some chips have protocol-specific image rejection calibrations programmed
741 * into their flash. This function will either get the value from flash and
742 * apply it, or run the image rejection algorithm to find the value.
743 *
744 * @deprecated Please use \ref RAIL_CalibrateIrAlt instead.
745 */
746 RAIL_Status_t RAIL_IEEE802154_CalibrateIrSubGhz(RAIL_Handle_t railHandle,
747 uint32_t *imageRejection);
748
749 /**
750 * Calibrates image rejection for Bluetooth Low Energy
751 *
752 * @param[in] railHandle A RAIL instance handle.
753 * @param[out] imageRejection The result of the image rejection calibration.
754 * @return A status code indicating success of the function call.
755 *
756 * Some chips have protocol-specific image rejection calibrations programmed
757 * into their flash. This function will either get the value from flash and
758 * apply it, or run the image rejection algorithm to find the value.
759 */
760 RAIL_Status_t RAIL_BLE_CalibrateIr(RAIL_Handle_t railHandle,
761 uint32_t *imageRejection);
762
763 /**
764 * Runs the temperature calibration.
765 *
766 * @param[in] railHandle A RAIL instance handle.
767 * @return A status code indicating success of the function call.
768 *
769 * Run the temperature calibration, which needs to recalibrate the synth if
770 * the temperature crosses 0C or the temperature delta since the last
771 * calibration exceeds 70C while in receive. RAIL will run the VCO calibration
772 * automatically upon entering receive or transmit states, so the application
773 * can omit this calibration if the stack re-enters receive or transmit with
774 * enough frequency to avoid reaching the temperature delta. If the application
775 * does not calibrate for temperature, it's possible to miss receive packets due
776 * to a drift in the carrier frequency.
777 *
778 * If multiple protocols are used, this function will return
779 * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
780 * not active. In that case, the calibration will be automatically performed
781 * next time the radio enters receive.
782 */
783 RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle);
784
785 /**
786 * Performs HFXO compensation.
787 *
788 * @param[in] railHandle A RAIL instance handle.
789 * @param[out] crystalPPMError Current deviation that has been corrected,
790 * measured in PPM. May be NULL.
791 * @return A status code indicating the result of the function call.
792 *
793 * Compute the PPM correction using the thermistor value available when
794 * \ref RAIL_EVENT_THERMISTOR_DONE occurs, after
795 * \ref RAIL_StartThermistorMeasurement() call.
796 * Then correct the RF frequency as well as Tx and Rx sampling.
797 *
798 * This function calls the following RAIL functions in sequence saving having
799 * to call them individually:
800 * - \ref RAIL_ConvertThermistorImpedance()
801 * - \ref RAIL_ComputeHFXOPPMError()
802 * - \ref RAIL_CompensateHFXO()
803 *
804 * @note This function makes the radio idle.
805 */
806 RAIL_Status_t RAIL_CalibrateHFXO(RAIL_Handle_t railHandle, int8_t *crystalPPMError);
807
808 /**
809 * @typedef RAIL_CalValues_t
810 * @brief A calibration value structure.
811 *
812 * This structure contains the set of persistent calibration values for
813 * EFR32. You can set these beforehand and apply them at startup to save the
814 * time required to compute them. Any of these values may be set to
815 * RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value.
816 */
817 typedef RAIL_IrCalValues_t RAIL_CalValues_t;
818
819 /**
820 * A define to set all RAIL_CalValues_t values to uninitialized.
821 *
822 * This define can be used when you have no data to pass to the calibration
823 * routines but wish to compute and save all possible calibrations.
824 */
825 #define RAIL_CALVALUES_UNINIT RAIL_IRCALVALUES_UNINIT
826
827 /** @} */ // end of group Calibration_EFR32
828
829 // -----------------------------------------------------------------------------
830 // Diagnostic
831 // -----------------------------------------------------------------------------
832 /**
833 * @addtogroup Diagnostic_EFR32 EFR32
834 * @{
835 * @brief Types specific to the EFR32 for the diagnostic routines.
836 * @ingroup Diagnostic
837 */
838
839 /**
840 * @typedef RAIL_FrequencyOffset_t
841 * @brief Chip-specific type that represents the number of Frequency Offset
842 * units. It is used with \ref RAIL_GetRxFreqOffset() and
843 * \ref RAIL_SetFreqOffset().
844 *
845 * The units on this chip are radio synthesizer resolution steps (synthTicks).
846 * On EFR32 (at least for now), the frequency offset is limited to 15 bits
847 * (size of SYNTH_CALOFFSET). A value of \ref RAIL_FREQUENCY_OFFSET_INVALID
848 * means that this value is invalid.
849 */
850 typedef int16_t RAIL_FrequencyOffset_t;
851
852 /**
853 * The maximum frequency offset value supported by this radio.
854 */
855 #define RAIL_FREQUENCY_OFFSET_MAX ((RAIL_FrequencyOffset_t) 0x3FFF)
856
857 /**
858 * The minimum frequency offset value supported by this radio.
859 */
860 #define RAIL_FREQUENCY_OFFSET_MIN ((RAIL_FrequencyOffset_t) -RAIL_FREQUENCY_OFFSET_MAX)
861
862 /**
863 * Specify an invalid frequency offset value. This will be returned if you
864 * call \ref RAIL_GetRxFreqOffset() at an invalid time.
865 */
866 #define RAIL_FREQUENCY_OFFSET_INVALID ((RAIL_FrequencyOffset_t) 0x8000)
867
868 /**
869 * @struct RAIL_DirectModeConfig_t
870 * @brief Chip-specific type that allows the user to specify direct mode
871 * parameters using \ref RAIL_ConfigDirectMode().
872 */
873 typedef struct RAIL_DirectModeConfig {
874 /** Enable synchronous RX DOUT using DCLK vs. asynchronous RX DOUT. */
875 bool syncRx;
876 /** Enable synchronous TX DIN using DCLK vs. asynchronous TX DIN. */
877 bool syncTx;
878
879 /** Only used with directRx */
880 /** Data output (DOUT) GPIO port */
881 uint8_t doutPort;
882 /** Data output (DOUT) GPIO pin */
883 uint8_t doutPin;
884
885 /** Only used in synchronous mode */
886 /** Data clock (DCLK) GPIO port. Only used in synchronous mode */
887 uint8_t dclkPort;
888 /** Data clock (DCLK) GPIO pin. Only used in synchronous mode */
889 uint8_t dclkPin;
890
891 /** Only used with directTx */
892 /** Data frame (DIN) GPIO port */
893 uint8_t dinPort;
894 /** Data frame (DIN) GPIO pin */
895 uint8_t dinPin;
896
897 /** Reserved for future use */
898 uint8_t reserved[3];
899 } RAIL_DirectModeConfig_t;
900
901 /** @} */ // end of group Diagnostic_EFR32
902
903 // -----------------------------------------------------------------------------
904 // Radio Configuration
905 // -----------------------------------------------------------------------------
906 /**
907 * @addtogroup Radio_Configuration_EFR32 EFR32
908 * @{
909 * @ingroup Radio_Configuration
910 * @brief Types specific to the EFR32 for radio configuration.
911 */
912
913 /**
914 * @brief The radio configuration structure.
915 *
916 * The radio configuration properly configures the
917 * radio for operation on a protocol. These configurations should not be
918 * created or edited by hand.
919 */
920 typedef const uint32_t *RAIL_RadioConfig_t;
921
922 /** @} */ // end of group Radio_Configuration_EFR32
923
924 // -----------------------------------------------------------------------------
925 // Transmit
926 // -----------------------------------------------------------------------------
927 /**
928 * @addtogroup PA_EFR32XG2X EFR32XG2X
929 * @{
930 * @ingroup PA
931 * @brief Types specific to the EFR32 for dealing with the on-chip PAs.
932 */
933
934 /**
935 * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher
936 * numerical value corresponds to a higher output power. These are referred to
937 * as 'raw (values/units)'. On EFR32, they can range from one of \ref
938 * RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MIN, or
939 * \ref RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN to one of \ref
940 * RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MAX, and \ref
941 * RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, respectively, depending on the selected \ref
942 * RAIL_TxPowerMode_t.
943 */
944 typedef uint8_t RAIL_TxPowerLevel_t;
945
946 /**
947 * PA power setting used directly by the \ref RAIL_GetPaPowerSetting() and
948 * \ref RAIL_SetPaPowerSetting() APIs which is decoded to the actual
949 * hardware register value(s).
950 */
951 typedef uint32_t RAIL_PaPowerSetting_t;
952
953 /**
954 * Returned by \ref RAIL_SetPaPowerSetting when the current PA does
955 * not support the dBm to power setting mapping table.
956 */
957 #define RAIL_TX_PA_POWER_SETTING_UNSUPPORTED (0U)
958
959 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1
960 /**
961 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
962 * RAIL_TX_POWER_MODE_2P4_HP mode.
963 */
964 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U)
965 /**
966 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
967 * RAIL_TX_POWER_MODE_2P4_HP mode.
968 */
969 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U)
970 /**
971 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
972 * RAIL_TX_POWER_MODE_2P4_MP mode.
973 */
974 #define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (90U)
975 /**
976 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
977 * RAIL_TX_POWER_MODE_2P4_MP mode.
978 */
979 #define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (1U)
980 /**
981 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
982 * RAIL_TX_POWER_MODE_2P4_LP mode.
983 */
984 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (64U)
985 /**
986 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
987 * RAIL_TX_POWER_MODE_2P4_LP mode.
988 */
989 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
990 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 4
991 /**
992 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
993 * RAIL_TX_POWER_MODE_2P4_HP mode.
994 * EFR32XG24: capable of 20dBm max output power has max powerlevel:180
995 * EFR32XG24: capable of 10dBm max output power has max powerlevel:90
996 */
997 #if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
998 && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10)
999 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U)
1000 #else
1001 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (90U)
1002 #endif
1003 /**
1004 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1005 * RAIL_TX_POWER_MODE_2P4_HP mode.
1006 */
1007 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U)
1008 /**
1009 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1010 * RAIL_TX_POWER_MODE_2P4_LP mode.
1011 */
1012 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U)
1013 /**
1014 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1015 * RAIL_TX_POWER_MODE_2P4_LP mode.
1016 */
1017 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
1018 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7))
1019 /**
1020 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1021 * RAIL_TX_POWER_MODE_2P4_HP mode.
1022 */
1023 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (127U)
1024 /**
1025 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1026 * RAIL_TX_POWER_MODE_2P4_HP mode.
1027 */
1028 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U)
1029 /**
1030 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1031 * RAIL_TX_POWER_MODE_2P4_LP mode.
1032 */
1033 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U)
1034 /**
1035 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1036 * RAIL_TX_POWER_MODE_2P4_LP mode.
1037 */
1038 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
1039 #else //efr32xg23
1040 /**
1041 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1042 * RAIL_TX_POWER_MODE_2P4_HP mode.
1043 */
1044 #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240)
1045 /**
1046 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1047 * RAIL_TX_POWER_MODE_2P4_HP mode.
1048 */
1049 #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U)
1050 /**
1051 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1052 * RAIL_TX_POWER_MODE_2P4_MP mode.
1053 */
1054 #define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
1055 /**
1056 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1057 * RAIL_TX_POWER_MODE_2P4_MP mode.
1058 */
1059 #define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
1060 /**
1061 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1062 * RAIL_TX_POWER_MODE_2P4_LP mode.
1063 */
1064 #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
1065 /**
1066 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1067 * RAIL_TX_POWER_MODE_2P4_LP mode.
1068 */
1069 #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
1070 /**
1071 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1072 * RAIL_TX_POWER_MODE_2P4_LLP mode.
1073 */
1074 #define RAIL_TX_POWER_LEVEL_2P4_LLP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
1075 /**
1076 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1077 * RAIL_TX_POWER_MODE_2P4_LLP mode.
1078 */
1079 #define RAIL_TX_POWER_LEVEL_2P4_LLP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
1080 #endif //_SILICON_LABS_32B_SERIES_2_CONFIG
1081
1082 #if RAIL_FEAT_SUBGIG_RADIO
1083 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1084 #ifndef RAIL_SUBGIG_MAX
1085 #define RAIL_SUBGIG_MAX 240U
1086 #endif
1087 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5
1088 #define RAIL_SUBGIG_MAX 79U
1089 #endif
1090 #define RAIL_SUBGIG_MIN 1U
1091
1092 /**
1093 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1094 * RAIL_TX_POWER_MODE_SUBGIG mode.
1095 */
1096 #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX)
1097 /**
1098 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1099 * RAIL_TX_POWER_MODE_SUBGIG mode.
1100 */
1101 #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN)
1102 /**
1103 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1104 * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
1105 */
1106 #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX)
1107 /**
1108 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1109 * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
1110 */
1111 #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN)
1112 /**
1113 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1114 * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
1115 */
1116 #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX)
1117 /**
1118 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1119 * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
1120 */
1121 #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN)
1122 /**
1123 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1124 * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
1125 */
1126 #define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX)
1127 /**
1128 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1129 * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
1130 */
1131 #define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (RAIL_SUBGIG_MIN)
1132 #if RAIL_SUPPORTS_EFF
1133 /**
1134 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1135 * RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM mode.
1136 */
1137 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_30DBM_MAX (RAIL_SUBGIG_MAX)
1138 /**
1139 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1140 * RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM mode.
1141 */
1142 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_30DBM_MIN (RAIL_SUBGIG_MIN)
1143 /**
1144 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1145 * RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM mode.
1146 */
1147 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_25DBM_MAX (RAIL_SUBGIG_MAX)
1148 /**
1149 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1150 * RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM mode.
1151 */
1152 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_25DBM_MIN (RAIL_SUBGIG_MIN)
1153 /**
1154 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1155 * RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM mode.
1156 */
1157 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_20DBM_MAX (RAIL_SUBGIG_MAX)
1158 /**
1159 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1160 * RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM mode.
1161 */
1162 #define RAIL_TX_POWER_LEVEL_SUBGIG_EFF_20DBM_MIN (RAIL_SUBGIG_MIN)
1163 #endif
1164 #endif //RAIL_FEAT_SUBGIG_RADIO
1165
1166 #if RAIL_SUPPORTS_OFDM_PA
1167 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 5
1168 #define RAIL_OFDM_PA_MAX 204U
1169 #define RAIL_OFDM_PA_EFF_MAX 204U
1170 #define RAIL_OFDM_PA_MULT 5U
1171 #define RAIL_OFDM_PA_MIN 0U
1172 #define RAIL_OFDM_PA_EFF_MIN 0U
1173 #endif
1174 /**
1175 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1176 * RAIL_TX_POWER_MODE_OFDM_PA mode.
1177 */
1178 #define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX)
1179 /**
1180 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1181 * RAIL_TX_POWER_MODE_OFDM_PA mode.
1182 */
1183 #define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN)
1184 #if RAIL_SUPPORTS_EFF
1185 /**
1186 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1187 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM mode.
1188 */
1189 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_30DBM_MAX (RAIL_OFDM_PA_EFF_MAX)
1190 /**
1191 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1192 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM mode.
1193 */
1194 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_30DBM_MIN (RAIL_OFDM_PA_EFF_MIN)
1195 /**
1196 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1197 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM mode.
1198 */
1199 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_25DBM_MAX (RAIL_OFDM_PA_EFF_MAX)
1200 /**
1201 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1202 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_250DBM mode.
1203 */
1204 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_25DBM_MIN (RAIL_OFDM_PA_EFF_MIN)
1205 /**
1206 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1207 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM mode.
1208 */
1209 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_20DBM_MAX (RAIL_OFDM_PA_EFF_MAX)
1210 /**
1211 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1212 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM mode.
1213 */
1214 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_20DBM_MIN (RAIL_OFDM_PA_EFF_MIN)
1215 /**
1216 * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1217 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode.
1218 */
1219 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MAX (RAIL_OFDM_PA_EFF_MAX)
1220 /**
1221 * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
1222 * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode.
1223 */
1224 #define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MIN (RAIL_OFDM_PA_EFF_MIN)
1225 #endif
1226 #endif //RAIL_SUPPORTS_OFDM_PA
1227
1228 /** Backwards compatability define */
1229 #define RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX
1230 /** Backwards compatability define */
1231 #define RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN
1232 /** Backwards compatability define */
1233 #define RAIL_TX_POWER_LEVEL_MP_MAX RAIL_TX_POWER_LEVEL_2P4_MP_MAX
1234 /** Backwards compatability define */
1235 #define RAIL_TX_POWER_LEVEL_MP_MIN RAIL_TX_POWER_LEVEL_2P4_MP_MIN
1236 /** Backwards compatability define */
1237 #define RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX
1238 /** Backwards compatability define */
1239 #define RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN
1240 /** Backwards compatability define */
1241 #define RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
1242 /** Backwards compatability define */
1243 #define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
1244
1245 /**
1246 * Invalid RAIL_TxPowerLevel_t value returned when an error occurs
1247 * with RAIL_GetTxPower.
1248 */
1249 #define RAIL_TX_POWER_LEVEL_INVALID (255U)
1250 /**
1251 * Sentinel value that can be passed to RAIL_SetTxPower to set
1252 * the highest power level available on the current PA, regardless
1253 * of which one is selected.
1254 */
1255 #define RAIL_TX_POWER_LEVEL_MAX (254U)
1256
1257 /**
1258 * @enum RAIL_TxPowerMode_t
1259 * @brief An enumeration of the EFR32 power modes.
1260 *
1261 * The power modes on the EFR32 correspond to the different on-chip PAs that
1262 * are available. For more information about the power and performance
1263 * characteristics of a given amplifier, see the data sheet.
1264 */
1265 #ifndef RAIL_INTERNAL_TXPOWERMODE
RAIL_ENUM(RAIL_TxPowerMode_t)1266 RAIL_ENUM(RAIL_TxPowerMode_t) {
1267 #if RAIL_FEAT_2G4_RADIO
1268 /**
1269 * High-power 2.4 GHz amplifier
1270 * EFR32XG21: up to 20 dBm, raw values: 1-180
1271 * EFR32XG22: up to 6 dBm, raw values: 1-128
1272 * EFR32XG24: capable of 20dBm max output power supports powerlevel: 0-180
1273 * EFR32XG24: capable of 10dBm max output power supports powerlevel: 0-90
1274 * EFR32XG28: capable of 10dBm max output power supports powerlevel: 0-240
1275 */
1276 RAIL_TX_POWER_MODE_2P4GIG_HP,
1277 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \
1278 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
1279 /**
1280 * Mid-power 2.4 GHz amplifier
1281 * EFR32XG21: up to 10 dBm, raw values: 1-90
1282 * EFR32XG22: N/A
1283 */
1284 RAIL_TX_POWER_MODE_2P4GIG_MP,
1285 #endif
1286 #if _SILICON_LABS_32B_SERIES_2_CONFIG != 3
1287 /**
1288 * Low-power 2.4 GHz amplifier
1289 * EFR32XG21: up to 0 dBm, raw values: 1-64
1290 * EFR32XG22: up to 0 dBm, raw values: 1-16
1291 * EFR32XG24: up to 0 dBm, raw values: 1-16
1292 */
1293 RAIL_TX_POWER_MODE_2P4GIG_LP,
1294 #endif
1295 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1296 /** Low-Low-power 2.4GHz amplifier */
1297 RAIL_TX_POWER_MODE_2P4GIG_LLP,
1298 #endif
1299 /** Select the highest power PA available on the current chip. */
1300 RAIL_TX_POWER_MODE_2P4GIG_HIGHEST,
1301 #endif
1302 #if RAIL_FEAT_SUBGIG_RADIO
1303 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1304 /** PA for all dBm values in range, using RAIL_PaPowerSetting_t table */
1305 RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE,
1306 #else
1307 /** High-power amplifier (Class D mode) */
1308 RAIL_TX_POWER_MODE_SUBGIG_HP,
1309 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_SUBGIG_HP instead. */
1310 RAIL_TX_POWER_MODE_SUBGIG = RAIL_TX_POWER_MODE_SUBGIG_HP,
1311 /** Mid-power amplifier */
1312 RAIL_TX_POWER_MODE_SUBGIG_MP,
1313 /** Low-power amplifier */
1314 RAIL_TX_POWER_MODE_SUBGIG_LP,
1315 /** Low-Low-power amplifier */
1316 RAIL_TX_POWER_MODE_SUBGIG_LLP,
1317 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1318 /** Select the highest power PA available on the current chip. */
1319 RAIL_TX_POWER_MODE_SUBGIG_HIGHEST,
1320 #endif//RAIL_FEAT_SUBGIG_RADIO
1321 #if RAIL_SUPPORTS_OFDM_PA
1322 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1323 /** PA for all dBm values in range, using RAIL_PaPowerSetting_t table */
1324 RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE,
1325 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE instead. */
1326 RAIL_TX_POWER_MODE_OFDM_PA,
1327 #else
1328 #error "RAIL_SUPPORTS_OFDM_PA is true, but there is no OFDM PA defined for this chip."
1329 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1330 #endif//RAIL_SUPPORTS_OFDM_PA
1331 #if RAIL_SUPPORTS_EFF
1332 //Added after the normal PAs so old code doesn't accidentally use the wrong PA
1333 #if RAIL_FEAT_SUBGIG_RADIO
1334 // EFF requires custom PAs. Normal PAs all use passthrough mode.
1335 /** Danger, may overtemp EFF. Use power protection! */
1336 RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM,
1337 /** Danger, may overtemp EFF. Use power protection! */
1338 RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM,
1339 /** Below 15 dBm use passthrough PAs */
1340 RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM,
1341 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1342 /** PA for all dBm values in range, for Front-End-Module, using RAIL_PaPowerSetting_t table */
1343 RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE,
1344 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1345 #endif//RAIL_FEAT_SUBGIG_RADIO
1346 #if RAIL_SUPPORTS_OFDM_PA
1347 // EFF requires custom PAs. Normal PAs all use passthrough mode.
1348 /** Danger, may overtemp EFF. Use power protection! */
1349 RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM,
1350 /** Danger, may overtemp EFF. Use power protection! */
1351 RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM,
1352 /** Below 15 dBm use passthrough PAs */
1353 RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM,
1354 /** Special PA sending full Sol output. Use carefully */
1355 RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM,
1356 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1357 /** PA for all dBm values in range, for Front-End-Module, using RAIL_PaPowerSetting_t table */
1358 RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE,
1359 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1360 #endif//RAIL_SUPPORTS_OFDM_PA
1361 #endif//RAIL_SUPPORTS_EFF
1362 /** Invalid amplifier Selection */
1363 RAIL_TX_POWER_MODE_NONE,
1364 };
1365 #endif //#ifndef RAIL_INTERNAL_TXPOWERMODE
1366
1367 #if RAIL_FEAT_2G4_RADIO
1368 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HP instead. */
1369 #define RAIL_TX_POWER_MODE_2P4_HP RAIL_TX_POWER_MODE_2P4GIG_HP
1370 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8))
1371 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_MP instead. */
1372 #define RAIL_TX_POWER_MODE_2P4_MP RAIL_TX_POWER_MODE_2P4GIG_MP
1373 #endif
1374 #if _SILICON_LABS_32B_SERIES_2_CONFIG != 3
1375 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_LP instead. */
1376 #define RAIL_TX_POWER_MODE_2P4_LP RAIL_TX_POWER_MODE_2P4GIG_LP
1377 #endif
1378 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1379 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_LLP instead. */
1380 #define RAIL_TX_POWER_MODE_2P4_LLP RAIL_TX_POWER_MODE_2P4GIG_LLP
1381 #endif
1382 /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST instead. */
1383 #define RAIL_TX_POWER_MODE_2P4_HIGHEST RAIL_TX_POWER_MODE_2P4GIG_HIGHEST
1384 #endif
1385
1386 /**
1387 * The number of PA's on this chip. (Including Virtual PAs)
1388 */
1389 #ifndef RAIL_NUM_PA
1390 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
1391 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
1392 || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7))
1393 #define RAIL_NUM_PA (2U)
1394 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
1395 #define RAIL_NUM_PA (4U)
1396 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)
1397 // There is a "dummy" PA for RAIL_TX_POWER_MODE_2P4GIG_HIGHEST which maps back to
1398 // RAIL_TX_POWER_MODE_2P4GIG_HP power curves. This explains why this value is 9 instead of 8.
1399 #define RAIL_NUM_PA (9U)
1400 #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
1401 #if RAIL_SUPPORTS_EFF
1402 #define RAIL_NUM_PA (13U)
1403 #else
1404 #define RAIL_NUM_PA (2U)
1405 #endif
1406 #else
1407 #define RAIL_NUM_PA (3U)
1408 #endif
1409 #endif //#ifndef RAIL_NUM_PA
1410
1411 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1412 // Self-referencing defines minimize compiler complaints when using RAIL_ENUM
1413 #if RAIL_FEAT_2G4_RADIO
1414 #ifndef RAIL_TX_POWER_MODE_2P4GIG_HP
1415 #define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP)
1416 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1417 #define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP)
1418 #endif //_SILICON_LABS_32B_SERIES_2_CONFIG == 1 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1419 #if _SILICON_LABS_32B_SERIES_2_CONFIG != 3
1420 #define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP)
1421 #endif //_SILICON_LABS_32B_SERIES_2_CONFIG != 3
1422 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1423 #define RAIL_TX_POWER_MODE_2P4GIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LLP)
1424 #endif // _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1425 #define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST)
1426 #endif //#ifndef RAIL_TX_POWER_MODE_2P4GIG_HP
1427 #endif //RAIL_FEAT_2G4_RADIO
1428
1429 #if RAIL_FEAT_SUBGIG_RADIO
1430 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1431 #define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)
1432 #else
1433 #define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP)
1434 #define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP)
1435 #define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP)
1436 #define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP)
1437 #define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG)
1438 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1439 #define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST)
1440 #if RAIL_SUPPORTS_EFF
1441 #define RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM)
1442 #define RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM)
1443 #define RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM)
1444 #define RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)
1445 #endif//RAIL_SUPPORTS_EFF
1446 #endif //RAIL_FEAT_SUBGIG_RADIO
1447 #if RAIL_SUPPORTS_OFDM_PA
1448 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1449 #define RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE)
1450 #define RAIL_TX_POWER_MODE_OFDM_PA ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA)
1451 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1452 #if RAIL_SUPPORTS_EFF
1453 #define RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM)
1454 #define RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM)
1455 #define RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM)
1456 #define RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM)
1457 #define RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE)
1458 #endif//RAIL_SUPPORTS_EFF
1459 #endif //RAIL_SUPPORTS_OFDM_PA
1460 #define RAIL_TX_POWER_MODE_NONE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_NONE)
1461 #endif//DOXYGEN_SHOULD_SKIP_THIS
1462
1463 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 5
1464 #if RAIL_SUPPORTS_EFF
1465 #define RAIL_POWER_MODE_IS_ANY_EFF(x) ( ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \
1466 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) \
1467 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM) \
1468 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM) \
1469 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM) \
1470 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM) \
1471 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM) \
1472 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM) \
1473 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM) \
1474 )
1475 #define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) ( ((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \
1476 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) )
1477 #define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_SUBGIG(x) ( ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) \
1478 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) )
1479 #define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) ( (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \
1480 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \
1481 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) \
1482 || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)) )
1483 #if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG
1484 // This macro is a boolean that checks for any OFDM modes
1485 #define RAIL_POWER_MODE_IS_ANY_OFDM(x) ( ((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \
1486 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \
1487 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM) \
1488 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM) \
1489 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM) \
1490 || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM) \
1491 )
1492 #endif
1493 #else
1494 #define RAIL_POWER_MODE_IS_ANY_EFF(x) (false)
1495 #if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG
1496 // This macro is a boolean that checks for any OFDM modes
1497 #define RAIL_POWER_MODE_IS_ANY_OFDM(x) ( ((x) == RAIL_TX_POWER_MODE_OFDM_PA) \
1498 )
1499 #endif
1500 #endif
1501 #endif
1502
1503 #ifndef RAIL_TX_POWER_MODE_NAMES_2P4GIG
1504 /**
1505 * @def RAIL_TX_POWER_MODE_NAMES_2P4GIG
1506 * @brief The names of the TX power modes for 2.4 GHz band.
1507 *
1508 * A list of the names for the TX power modes on the EFR32 series 2 parts
1509 * supporting 2.4 GHz operation.
1510 * This macro is useful for test applications and debugging output.
1511 */
1512 #if RAIL_FEAT_2G4_RADIO
1513 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 1
1514 #define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
1515 "RAIL_TX_POWER_MODE_2P4GIG_HP", \
1516 "RAIL_TX_POWER_MODE_2P4GIG_MP", \
1517 "RAIL_TX_POWER_MODE_2P4GIG_LP", \
1518 "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
1519 #elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1520 #define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
1521 "RAIL_TX_POWER_MODE_2P4GIG_HP", \
1522 "RAIL_TX_POWER_MODE_2P4GIG_MP", \
1523 "RAIL_TX_POWER_MODE_2P4GIG_LP", \
1524 "RAIL_TX_POWER_MODE_2P4GIG_LLP", \
1525 "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
1526 #else // (_SILICON_LABS_32B_SERIES_2_CONFIG == 2|4|7)
1527 #define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
1528 "RAIL_TX_POWER_MODE_2P4GIG_HP", \
1529 "RAIL_TX_POWER_MODE_2P4GIG_LP", \
1530 "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
1531 #endif
1532 #else
1533 #define RAIL_TX_POWER_MODE_NAMES_2P4GIG
1534 #endif //RAIL_FEAT_2G4_RADIO
1535 #endif
1536
1537 /**
1538 * @def RAIL_TX_POWER_MODE_NAMES_SUBGIG
1539 * @brief The names of the TX power modes for Sub-GHz band.
1540 *
1541 * A list of the names for the TX power modes on the EFR32 series 2 parts
1542 * supporting Sub-GHz operation.
1543 * This macro is useful for test applications and debugging output.
1544 */
1545 #if RAIL_FEAT_SUBGIG_RADIO
1546 #if RAIL_SUPPORTS_EFF
1547 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG \
1548 "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE", \
1549 "RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM", \
1550 "RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM", \
1551 "RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM", \
1552 "RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE",
1553 #else
1554 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1555 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG \
1556 "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE",
1557 #else
1558 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG \
1559 "RAIL_TX_POWER_MODE_SUBGIG_HP", \
1560 "RAIL_TX_POWER_MODE_SUBGIG_MP", \
1561 "RAIL_TX_POWER_MODE_SUBGIG_LP", \
1562 "RAIL_TX_POWER_MODE_SUBGIG_LLP", \
1563 "RAIL_TX_POWER_MODE_SUBGIG_HIGHEST",
1564 #endif //RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1565 #endif //
1566 #else
1567 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG
1568 #endif
1569
1570 /**
1571 * @def RAIL_TX_POWER_MODE_NAMES_OFDM_PA
1572 * @brief The names of the TX power modes for the OFDM PA.
1573 *
1574 * A list of the names for the TX power modes on EFR32 series 2 parts
1575 * with an OFDM PA.
1576 * This macro is useful for test applications and debugging output.
1577 */
1578 #if RAIL_SUPPORTS_OFDM_PA
1579 #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA \
1580 "RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE",
1581 #else
1582 #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA
1583 #endif
1584
1585 /**
1586 * @def RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF
1587 * @brief The names of the TX power modes for Sub-GHz band with an EFF.
1588 *
1589 * A list of the names for the Sub-GHz TX power modes on EFR32 series 2 parts
1590 * with an EFF.
1591 * This macro is useful for test applications and debugging output.
1592 */
1593 #if RAIL_SUPPORTS_EFF
1594 #if RAIL_FEAT_SUBGIG_RADIO
1595 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF \
1596 "RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM", \
1597 "RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM", \
1598 "RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM", \
1599 "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE", \
1600 "RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE",
1601 #else
1602 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF
1603 #endif
1604 #else
1605 #define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF
1606 #endif//RAIL_SUPPORTS_EFF
1607
1608 /**
1609 * @def RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF
1610 * @brief The names of the TX power modes for the OFDM PA with an EFF.
1611 *
1612 * A list of the names for the TX power modes on EFR32 series 2 parts
1613 * with an OFDM PA and EFF.
1614 * This macro is useful for test applications and debugging output.
1615 */
1616 #if RAIL_SUPPORTS_EFF
1617 #if RAIL_SUPPORTS_OFDM_PA
1618 #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF \
1619 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM", \
1620 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM", \
1621 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM", \
1622 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM", \
1623 "RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE", \
1624 "RAIL_TX_POWER_MODE_OFDM_PA", \
1625 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE",
1626 #else
1627 #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF
1628 #endif
1629 #else
1630 #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF
1631 #endif//RAIL_SUPPORTS_EFF
1632
1633 #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE
1634 #define RAIL_TX_POWER_MODE_NAMES { \
1635 "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE", \
1636 "RAIL_TX_POWER_MODE_SUBGIG_HIGHEST", \
1637 "RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE", \
1638 "RAIL_TX_POWER_MODE_OFDM_PA", \
1639 "RAIL_TX_POWER_MODE_SUBGIG_EFF_30DBM", \
1640 "RAIL_TX_POWER_MODE_SUBGIG_EFF_25DBM", \
1641 "RAIL_TX_POWER_MODE_SUBGIG_EFF_20DBM", \
1642 "RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE", \
1643 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM", \
1644 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_25DBM", \
1645 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_20DBM", \
1646 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM", \
1647 "RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE", \
1648 "RAIL_TX_POWER_MODE_NONE", \
1649 }
1650 #else
1651 /**
1652 * @def RAIL_TX_POWER_MODE_NAMES
1653 * @brief The names of the TX power modes
1654 *
1655 * A list of the names for the TX power modes on the EFR32 series 2 parts. This
1656 * macro is useful for test applications and debugging output.
1657 */
1658 #define RAIL_TX_POWER_MODE_NAMES { \
1659 RAIL_TX_POWER_MODE_NAMES_2P4GIG \
1660 RAIL_TX_POWER_MODE_NAMES_SUBGIG \
1661 RAIL_TX_POWER_MODE_NAMES_OFDM_PA \
1662 RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF \
1663 RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF \
1664 "RAIL_TX_POWER_MODE_NONE" \
1665 }
1666 #endif
1667
1668 /**
1669 * @struct RAIL_TxPowerConfig_t
1670 *
1671 * @brief A structure containing values used to initialize the power amplifiers.
1672 */
1673 typedef struct RAIL_TxPowerConfig {
1674 /** TX power mode */
1675 RAIL_TxPowerMode_t mode;
1676 /** Power amplifier supply voltage in mV, generally:
1677 * DCDC supply ~ 1800 mV (1.8 V)
1678 * Battery supply ~ 3300 mV (3.3 V)
1679 */
1680 uint16_t voltage;
1681 /** The amount of time to spend ramping for TX in uS. */
1682 uint16_t rampTime;
1683 } RAIL_TxPowerConfig_t;
1684
1685 /** @} */ // end of group PA_EFR32
1686
1687 // -----------------------------------------------------------------------------
1688 // PTI
1689 // -----------------------------------------------------------------------------
1690 /**
1691 * @addtogroup PTI_EFR32 EFR32
1692 * @{
1693 * @brief EFR32 PTI functionality
1694 * @ingroup PTI
1695 *
1696 * These enumerations and structures are used with RAIL PTI API. EFR32 supports
1697 * SPI and UART PTI and is configurable in terms of baud rates and pin PTI
1698 * pin locations.
1699 */
1700
1701 /** A channel type enumeration. */
RAIL_ENUM(RAIL_PtiMode_t)1702 RAIL_ENUM(RAIL_PtiMode_t) {
1703 /** Turn PTI off entirely. */
1704 RAIL_PTI_MODE_DISABLED,
1705 /** SPI mode. */
1706 RAIL_PTI_MODE_SPI,
1707 /** UART mode. */
1708 RAIL_PTI_MODE_UART,
1709 /** 9-bit UART mode. */
1710 RAIL_PTI_MODE_UART_ONEWIRE,
1711 };
1712
1713 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1714 // Self-referencing defines minimize compiler complaints when using RAIL_ENUM
1715 #define RAIL_PTI_MODE_DISABLED ((RAIL_PtiMode_t) RAIL_PTI_MODE_DISABLED)
1716 #define RAIL_PTI_MODE_SPI ((RAIL_PtiMode_t) RAIL_PTI_MODE_SPI)
1717 #define RAIL_PTI_MODE_UART ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART)
1718 #define RAIL_PTI_MODE_UART_ONEWIRE ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART_ONEWIRE)
1719 #endif//DOXYGEN_SHOULD_SKIP_THIS
1720
1721 /**
1722 * @struct RAIL_PtiConfig_t
1723 * @brief A configuration for PTI.
1724 */
1725 typedef struct RAIL_PtiConfig {
1726 /** Packet Trace mode (UART or SPI) */
1727 RAIL_PtiMode_t mode;
1728 /** Output baudrate for PTI in Hz */
1729 uint32_t baud;
1730 /** Data output (DOUT) location for pin/port */
1731 uint8_t doutLoc;
1732 /** Data output (DOUT) GPIO port */
1733 uint8_t doutPort;
1734 /** Data output (DOUT) GPIO pin */
1735 uint8_t doutPin;
1736 /** Data clock (DCLK) location for pin/port. Only used in SPI mode */
1737 uint8_t dclkLoc;
1738 /** Data clock (DCLK) GPIO port. Only used in SPI mode */
1739 uint8_t dclkPort;
1740 /** Data clock (DCLK) GPIO pin. Only used in SPI mode */
1741 uint8_t dclkPin;
1742 /** Data frame (DFRAME) location for pin/port */
1743 uint8_t dframeLoc;
1744 /** Data frame (DFRAME) GPIO port */
1745 uint8_t dframePort;
1746 /** Data frame (DFRAME) GPIO pin */
1747 uint8_t dframePin;
1748 } RAIL_PtiConfig_t;
1749
1750 /** @} */ // end of group PTI_EFR32
1751
1752 /******************************************************************************
1753 * Calibration Structures
1754 *****************************************************************************/
1755 /**
1756 * @addtogroup Calibration
1757 * @{
1758 */
1759
1760 /// Use this value with either TX or RX values in RAIL_SetPaCTune
1761 /// to use whatever value is already set and do no update. This
1762 /// value is provided to provide consistency across EFR32 chips,
1763 /// but technically speaking, all PA capacitance tuning values are
1764 /// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported
1765 /// on those parts.
1766 #define RAIL_PACTUNE_IGNORE (255U)
1767
1768 /** @} */ // end of group Calibration
1769
1770 // -----------------------------------------------------------------------------
1771 // Retiming
1772 // -----------------------------------------------------------------------------
1773 /**
1774 * @addtogroup Retiming_EFR32 Retiming
1775 * @{
1776 * @brief EFR32-specific retiming capability.
1777 * @ingroup RAIL_API
1778 *
1779 * The EFR product families have many digital and analog modules that can run
1780 * in parallel with a radio. Such combinations can result in interference and
1781 * degradation on the radio RX sensitivity. Retiming have the capability to
1782 * modify the clocking of the digital modules to reduce such interference.
1783 */
1784
1785 /**
1786 * @enum RAIL_RetimeOptions_t
1787 * @brief Retiming options bit shifts.
1788 */
RAIL_ENUM(RAIL_RetimeOptions_t)1789 RAIL_ENUM(RAIL_RetimeOptions_t) {
1790 /** Shift position of \ref RAIL_RETIME_OPTION_HFXO bit */
1791 RAIL_RETIME_OPTION_HFXO_SHIFT = 0,
1792 /** Shift position of \ref RAIL_RETIME_OPTION_HFRCO bit */
1793 RAIL_RETIME_OPTION_HFRCO_SHIFT,
1794 /** Shift position of \ref RAIL_RETIME_OPTION_DCDC bit */
1795 RAIL_RETIME_OPTION_DCDC_SHIFT,
1796 /** Shift position of \ref RAIL_RETIME_OPTION_LCD bit */
1797 RAIL_RETIME_OPTION_LCD_SHIFT,
1798 };
1799
1800 // RAIL_RetimeOptions_t bitmasks
1801 /**
1802 * An option to configure HFXO retiming
1803 */
1804 #define RAIL_RETIME_OPTION_HFXO \
1805 (1U << RAIL_RETIME_OPTION_HFXO_SHIFT)
1806
1807 /**
1808 * An option to configure HFRCO retiming
1809 */
1810 #define RAIL_RETIME_OPTION_HFRCO \
1811 (1U << RAIL_RETIME_OPTION_HFRCO_SHIFT)
1812
1813 /**
1814 * An option to configure DCDC retiming
1815 */
1816 #define RAIL_RETIME_OPTION_DCDC \
1817 (1U << RAIL_RETIME_OPTION_DCDC_SHIFT)
1818
1819 /**
1820 * An option to configure LCD retiming
1821 */
1822 #define RAIL_RETIME_OPTION_LCD \
1823 (1U << RAIL_RETIME_OPTION_LCD_SHIFT)
1824
1825 /** A value representing no retiming options */
1826 #define RAIL_RETIME_OPTIONS_NONE 0x0U
1827
1828 /** A value representing all retiming options */
1829 #define RAIL_RETIME_OPTIONS_ALL 0xFFU
1830
1831 /**
1832 * Configure retiming options.
1833 *
1834 * @param[in] railHandle A handle of RAIL instance.
1835 * @param[in] mask A bitmask containing which options should be modified.
1836 * @param[in] options A bitmask containing desired configuration settings.
1837 * Bit positions for each option are found in the \ref RAIL_RetimeOptions_t.
1838 * @return Status code indicating success of the function call.
1839 */
1840 RAIL_Status_t RAIL_ConfigRetimeOptions(RAIL_Handle_t railHandle,
1841 RAIL_RetimeOptions_t mask,
1842 RAIL_RetimeOptions_t options);
1843
1844 /**
1845 * Gets currently configured retiming option.
1846 *
1847 * @param[in] railHandle A handle of RAIL instance.
1848 * @param[out] pOptions A pointer to configured retiming options
1849 bitmask indicating which are enabled.
1850 * @return Status code indicating success of the function call.
1851 */
1852 RAIL_Status_t RAIL_GetRetimeOptions(RAIL_Handle_t railHandle,
1853 RAIL_RetimeOptions_t *pOptions);
1854
1855 /**
1856 * Indicate that the DCDC peripheral bus clock enable has changed allowing
1857 * RAIL to react accordingly.
1858 *
1859 * @note This should be called after DCDC has been enabled or disabled.
1860 *
1861 * @return Status code indicating success of the function call.
1862 */
1863 RAIL_Status_t RAIL_ChangedDcdc(void);
1864
1865 /** @} */ // end of group Retiming_EFR32
1866
1867 /******************************************************************************
1868 * RX Channel Hopping
1869 *****************************************************************************/
1870 /**
1871 * @addtogroup Rx_Channel_Hopping RX Channel Hopping
1872 * @{
1873 */
1874
1875 #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8
1876 /// The static amount of memory needed per channel for channel hopping, measured
1877 /// in 32 bit words, regardless of the size of radio configuration structures.
1878 #define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (61U)
1879 #else
1880 /// The static amount of memory needed per channel for channel hopping, measured
1881 /// in 32 bit words, regardless of the size of radio configuration structures.
1882 #define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (54U)
1883
1884 #endif
1885
1886 /** @} */ // end of group Rx_Channel_Hopping
1887
1888 /**
1889 * @addtogroup Sleep
1890 * @{
1891 */
1892
1893 /// Default PRS channel to use when configuring sleep
1894 #define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U)
1895
1896 #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7))
1897 /// Default RTCC channel to use when configuring sleep
1898 #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U)
1899 #else
1900 /// Default RTCC channel to use when configuring sleep
1901 #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U)
1902 #endif
1903
1904 /// Default timer synchronization configuration
1905 #define RAIL_TIMER_SYNC_DEFAULT { \
1906 RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \
1907 RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \
1908 RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \
1909 }
1910
1911 /** @} */ // end of group Sleep
1912
1913 /**
1914 * @addtogroup Data_Management_EFR32XG2X EFR32XG2X
1915 * @{
1916 * @ingroup Data_Management
1917 */
1918
1919 /// Fixed-width type indicating the needed alignment for RX and TX FIFOs. Note
1920 /// that docs.silabs.com will incorrectly indicate that this is always a
1921 /// uint8_t, but it does vary across RAIL platforms.
1922 #if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
1923 #define RAIL_FIFO_ALIGNMENT_TYPE uint32_t
1924 #else
1925 #define RAIL_FIFO_ALIGNMENT_TYPE uint8_t
1926 #endif
1927
1928 /// Alignment that is needed for the RX and TX FIFOs.
1929 #define RAIL_FIFO_ALIGNMENT (sizeof(RAIL_FIFO_ALIGNMENT_TYPE))
1930
1931 /** @} */ // end of group Data_Management_EFR32
1932
1933 /**
1934 * @addtogroup State_Transitions_EFR32XG2X
1935 * @{
1936 * @ingroup State_Transitions
1937 */
1938
1939 /**
1940 * @def RAIL_MINIMUM_TRANSITION_US
1941 * @brief The minimum value for a consistent RAIL transition
1942 * @note Transitions may need to be slower than this when using longer
1943 * \ref RAIL_TxPowerConfig_t::rampTime values
1944 */
1945 #define RAIL_MINIMUM_TRANSITION_US (100U)
1946
1947 /**
1948 * @def RAIL_MAXIMUM_TRANSITION_US
1949 * @brief The maximum value for a consistent RAIL transition
1950 */
1951 #define RAIL_MAXIMUM_TRANSITION_US (1000000U)
1952
1953 /**
1954 * @typedef RAIL_TransitionTime_t
1955 * @brief Suitable type for the supported transition time range.
1956 */
1957 typedef uint32_t RAIL_TransitionTime_t;
1958
1959 /** @} */ // end of group State_Transitions_EFR32
1960
1961 #ifdef __cplusplus
1962 }
1963 #endif
1964
1965 #endif //__RAIL_TYPES_H__
1966
1967 #endif //__RAIL_CHIP_SPECIFIC_H_
1968
