1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/toolchain.h> 8 #include <zephyr/linker/sections.h> 9 #include <zephyr/arch/cpu.h> 10 #include <zephyr/sys/barrier.h> 11 z_arm64_el3_plat_init(void)12void z_arm64_el3_plat_init(void) 13 { 14 uint64_t reg, val; 15 16 /* Enable access control configuration from lower EL */ 17 reg = read_actlr_el3(); 18 reg |= (ACTLR_EL3_L2ACTLR_BIT | 19 ACTLR_EL3_L2ECTLR_BIT | 20 ACTLR_EL3_L2CTLR_BIT | 21 ACTLR_EL3_CPUACTLR_BIT | 22 ACTLR_EL3_CPUECTLR_BIT); 23 write_actlr_el3(reg); 24 25 reg = read_sysreg(CORTEX_A72_L2ACTLR_EL1); 26 reg |= CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT; 27 write_sysreg(reg, CORTEX_A72_L2ACTLR_EL1); 28 29 val = ((CORTEX_A72_L2_DATA_RAM_LATENCY_MASK << 30 CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | 31 (CORTEX_A72_L2_TAG_RAM_LATENCY_MASK << 32 CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT) | 33 (CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE << 34 CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | 35 (CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE << 36 CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT)); 37 38 reg &= ~val; 39 40 val = ((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << 41 CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | 42 (CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE << 43 CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | 44 (CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE << 45 CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT)); 46 47 reg |= val; 48 49 write_sysreg(reg, CORTEX_A72_L2CTLR_EL1); 50 51 barrier_dsync_fence_full(); 52 barrier_isync_fence_full(); 53 } 54
