1 /*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch_helpers.h>
11 #include <bl32/sp_min/platform_sp_min.h>
12 #include <common/debug.h>
13 #include <drivers/arm/gic_common.h>
14 #include <drivers/arm/gicv2.h>
15 #include <drivers/clk.h>
16 #include <dt-bindings/clock/stm32mp1-clks.h>
17 #include <lib/mmio.h>
18 #include <lib/psci/psci.h>
19 #include <plat/common/platform.h>
20
21 #include <platform_def.h>
22
23 static uintptr_t stm32_sec_entrypoint;
24 static uint32_t cntfrq_core0;
25
26 /*******************************************************************************
27 * STM32MP1 handler called when a CPU is about to enter standby.
28 * call by core 1 to enter in wfi
29 ******************************************************************************/
stm32_cpu_standby(plat_local_state_t cpu_state)30 static void stm32_cpu_standby(plat_local_state_t cpu_state)
31 {
32 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT;
33
34 assert(cpu_state == ARM_LOCAL_STATE_RET);
35
36 /*
37 * Enter standby state
38 * dsb is good practice before using wfi to enter low power states
39 */
40 isb();
41 dsb();
42 while (interrupt == GIC_SPURIOUS_INTERRUPT) {
43 wfi();
44
45 /* Acknowledge IT */
46 interrupt = gicv2_acknowledge_interrupt();
47 /* If Interrupt == 1022 it will be acknowledged by non secure */
48 if ((interrupt != PENDING_G1_INTID) &&
49 (interrupt != GIC_SPURIOUS_INTERRUPT)) {
50 gicv2_end_of_interrupt(interrupt);
51 }
52 }
53 }
54
55 /*******************************************************************************
56 * STM32MP1 handler called when a power domain is about to be turned on. The
57 * mpidr determines the CPU to be turned on.
58 * call by core 0 to activate core 1
59 ******************************************************************************/
stm32_pwr_domain_on(u_register_t mpidr)60 static int stm32_pwr_domain_on(u_register_t mpidr)
61 {
62 unsigned long current_cpu_mpidr = read_mpidr_el1();
63 uintptr_t bkpr_core1_addr =
64 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
65 uintptr_t bkpr_core1_magic =
66 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
67
68 if (mpidr == current_cpu_mpidr) {
69 return PSCI_E_INVALID_PARAMS;
70 }
71
72 /* Only one valid entry point */
73 if (stm32_sec_entrypoint != (uintptr_t)&sp_min_warm_entrypoint) {
74 return PSCI_E_INVALID_ADDRESS;
75 }
76
77 clk_enable(RTCAPB);
78
79 cntfrq_core0 = read_cntfrq_el0();
80
81 /* Write entrypoint in backup RAM register */
82 mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint);
83
84 /* Write magic number in backup register */
85 mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
86
87 clk_disable(RTCAPB);
88
89 /* Generate an IT to core 1 */
90 gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, false, STM32MP_SECONDARY_CPU);
91
92 return PSCI_E_SUCCESS;
93 }
94
95 /*******************************************************************************
96 * STM32MP1 handler called when a power domain is about to be turned off. The
97 * target_state encodes the power state that each level should transition to.
98 ******************************************************************************/
stm32_pwr_domain_off(const psci_power_state_t * target_state)99 static void stm32_pwr_domain_off(const psci_power_state_t *target_state)
100 {
101 /* Nothing to do */
102 }
103
104 /*******************************************************************************
105 * STM32MP1 handler called when a power domain is about to be suspended. The
106 * target_state encodes the power state that each level should transition to.
107 ******************************************************************************/
stm32_pwr_domain_suspend(const psci_power_state_t * target_state)108 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
109 {
110 /* Nothing to do, power domain is not disabled */
111 }
112
113 /*******************************************************************************
114 * STM32MP1 handler called when a power domain has just been powered on after
115 * being turned off earlier. The target_state encodes the low power state that
116 * each level has woken up from.
117 * call by core 1 just after wake up
118 ******************************************************************************/
stm32_pwr_domain_on_finish(const psci_power_state_t * target_state)119 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
120 {
121 stm32mp_gic_pcpu_init();
122
123 write_cntfrq_el0(cntfrq_core0);
124 }
125
126 /*******************************************************************************
127 * STM32MP1 handler called when a power domain has just been powered on after
128 * having been suspended earlier. The target_state encodes the low power state
129 * that each level has woken up from.
130 ******************************************************************************/
stm32_pwr_domain_suspend_finish(const psci_power_state_t * target_state)131 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t
132 *target_state)
133 {
134 /* Nothing to do, power domain is not disabled */
135 }
136
stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t * target_state)137 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
138 *target_state)
139 {
140 ERROR("stm32mpu1 Power Down WFI: operation not handled.\n");
141 panic();
142 }
143
stm32_system_off(void)144 static void __dead2 stm32_system_off(void)
145 {
146 ERROR("stm32mpu1 System Off: operation not handled.\n");
147 panic();
148 }
149
stm32_system_reset(void)150 static void __dead2 stm32_system_reset(void)
151 {
152 mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR,
153 RCC_MP_GRSTCSETR_MPSYSRST);
154
155 /* Loop in case system reset is not immediately caught */
156 for ( ; ; ) {
157 ;
158 }
159 }
160
stm32_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)161 static int stm32_validate_power_state(unsigned int power_state,
162 psci_power_state_t *req_state)
163 {
164 if (psci_get_pstate_type(power_state) != 0U) {
165 return PSCI_E_INVALID_PARAMS;
166 }
167
168 if (psci_get_pstate_pwrlvl(power_state) != 0U) {
169 return PSCI_E_INVALID_PARAMS;
170 }
171
172 if (psci_get_pstate_id(power_state) != 0U) {
173 return PSCI_E_INVALID_PARAMS;
174 }
175
176 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET;
177 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN;
178
179 return PSCI_E_SUCCESS;
180 }
181
stm32_validate_ns_entrypoint(uintptr_t entrypoint)182 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
183 {
184 /* The non-secure entry point must be in DDR */
185 if (entrypoint < STM32MP_DDR_BASE) {
186 return PSCI_E_INVALID_ADDRESS;
187 }
188
189 return PSCI_E_SUCCESS;
190 }
191
stm32_node_hw_state(u_register_t target_cpu,unsigned int power_level)192 static int stm32_node_hw_state(u_register_t target_cpu,
193 unsigned int power_level)
194 {
195 /*
196 * The format of 'power_level' is implementation-defined, but 0 must
197 * mean a CPU. Only allow level 0.
198 */
199 if (power_level != MPIDR_AFFLVL0) {
200 return PSCI_E_INVALID_PARAMS;
201 }
202
203 /*
204 * From psci view the CPU 0 is always ON,
205 * CPU 1 can be SUSPEND or RUNNING.
206 * Therefore do not manage POWER OFF state and always return HW_ON.
207 */
208
209 return (int)HW_ON;
210 }
211
212 /*******************************************************************************
213 * Export the platform handlers. The ARM Standard platform layer will take care
214 * of registering the handlers with PSCI.
215 ******************************************************************************/
216 static const plat_psci_ops_t stm32_psci_ops = {
217 .cpu_standby = stm32_cpu_standby,
218 .pwr_domain_on = stm32_pwr_domain_on,
219 .pwr_domain_off = stm32_pwr_domain_off,
220 .pwr_domain_suspend = stm32_pwr_domain_suspend,
221 .pwr_domain_on_finish = stm32_pwr_domain_on_finish,
222 .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish,
223 .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi,
224 .system_off = stm32_system_off,
225 .system_reset = stm32_system_reset,
226 .validate_power_state = stm32_validate_power_state,
227 .validate_ns_entrypoint = stm32_validate_ns_entrypoint,
228 .get_node_hw_state = stm32_node_hw_state
229 };
230
231 /*******************************************************************************
232 * Export the platform specific power ops.
233 ******************************************************************************/
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)234 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
235 const plat_psci_ops_t **psci_ops)
236 {
237 stm32_sec_entrypoint = sec_entrypoint;
238 *psci_ops = &stm32_psci_ops;
239
240 return 0;
241 }
242
