1 /*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <drivers/ti/uart/uart_16550.h>
18 #include <lib/mmio.h>
19 #include <plat_private.h>
20 #include <plat/common/platform.h>
21
22 static entry_point_info_t bl33_ep_info;
23
24 /*******************************************************************************
25 * Return a pointer to the 'entry_point_info' structure of the next image for
26 * the security state specified. BL33 corresponds to the non-secure image type.
27 * A NULL pointer is returned if the image does not exist.
28 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)29 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
30 {
31 entry_point_info_t *next_image_info;
32
33 next_image_info = &bl33_ep_info;
34
35 if (next_image_info->pc == 0U) {
36 return NULL;
37 }
38
39 return next_image_info;
40 }
41
42 #pragma weak params_early_setup
params_early_setup(u_register_t plat_param_from_bl2)43 void params_early_setup(u_register_t plat_param_from_bl2)
44 {
45 }
46
47 unsigned int plat_is_my_cpu_primary(void);
48
49 /*******************************************************************************
50 * Perform any BL32 specific platform actions.
51 ******************************************************************************/
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)52 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
53 u_register_t arg2, u_register_t arg3)
54 {
55 static console_t console;
56
57 params_early_setup(arg1);
58
59 if (rockchip_get_uart_base() != 0)
60 console_16550_register(rockchip_get_uart_base(),
61 rockchip_get_uart_clock(),
62 rockchip_get_uart_baudrate(), &console);
63
64 VERBOSE("sp_min_setup\n");
65
66 bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
67 }
68
69 /*******************************************************************************
70 * Perform any sp_min platform setup code
71 ******************************************************************************/
sp_min_platform_setup(void)72 void sp_min_platform_setup(void)
73 {
74 generic_delay_timer_init();
75 plat_rockchip_soc_init();
76
77 /* Initialize the gic cpu and distributor interfaces */
78 plat_rockchip_gic_driver_init();
79 plat_rockchip_gic_init();
80 plat_rockchip_pmu_init();
81 }
82
83 /*******************************************************************************
84 * Perform the very early platform specific architectural setup here. At the
85 * moment this is only initializes the mmu in a quick and dirty way.
86 ******************************************************************************/
sp_min_plat_arch_setup(void)87 void sp_min_plat_arch_setup(void)
88 {
89 plat_cci_init();
90 plat_cci_enable();
91
92 plat_configure_mmu_svc_mon(BL_CODE_BASE,
93 BL_COHERENT_RAM_END - BL_CODE_BASE,
94 BL_CODE_BASE,
95 BL_CODE_END,
96 BL_COHERENT_RAM_BASE,
97 BL_COHERENT_RAM_END);
98 }
99
sp_min_plat_fiq_handler(uint32_t id)100 void sp_min_plat_fiq_handler(uint32_t id)
101 {
102 VERBOSE("[sp_min] interrupt #%d\n", id);
103 }
104
