1 /*
2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <lib/mmio.h>
8
9 #include "agilex_pinmux.h"
10 #include "agilex_system_manager.h"
11
12 const uint32_t sysmgr_pinmux_array_sel[] = {
13 0x00000000, 0x00000001, /* usb */
14 0x00000004, 0x00000001,
15 0x00000008, 0x00000001,
16 0x0000000c, 0x00000001,
17 0x00000010, 0x00000001,
18 0x00000014, 0x00000001,
19 0x00000018, 0x00000001,
20 0x0000001c, 0x00000001,
21 0x00000020, 0x00000001,
22 0x00000024, 0x00000001,
23 0x00000028, 0x00000001,
24 0x0000002c, 0x00000001,
25 0x00000030, 0x00000000, /* emac0 */
26 0x00000034, 0x00000000,
27 0x00000038, 0x00000000,
28 0x0000003c, 0x00000000,
29 0x00000040, 0x00000000,
30 0x00000044, 0x00000000,
31 0x00000048, 0x00000000,
32 0x0000004c, 0x00000000,
33 0x00000050, 0x00000000,
34 0x00000054, 0x00000000,
35 0x00000058, 0x00000000,
36 0x0000005c, 0x00000000,
37 0x00000060, 0x00000008, /* gpio1 */
38 0x00000064, 0x00000008,
39 0x00000068, 0x00000005, /* uart0 tx */
40 0x0000006c, 0x00000005, /* uart 0 rx */
41 0x00000070, 0x00000008, /* gpio */
42 0x00000074, 0x00000008,
43 0x00000078, 0x00000004, /* i2c1 */
44 0x0000007c, 0x00000004,
45 0x00000080, 0x00000007, /* jtag */
46 0x00000084, 0x00000007,
47 0x00000088, 0x00000007,
48 0x0000008c, 0x00000007,
49 0x00000090, 0x00000001, /* sdmmc data0 */
50 0x00000094, 0x00000001,
51 0x00000098, 0x00000001,
52 0x0000009c, 0x00000001,
53 0x00000100, 0x00000001,
54 0x00000104, 0x00000001, /* sdmmc.data3 */
55 0x00000108, 0x00000008, /* loan */
56 0x0000010c, 0x00000008, /* gpio */
57 0x00000110, 0x00000008,
58 0x00000114, 0x00000008, /* gpio1.io21 */
59 0x00000118, 0x00000005, /* mdio0.mdio */
60 0x0000011c, 0x00000005 /* mdio0.mdc */
61 };
62
63 const uint32_t sysmgr_pinmux_array_ctrl[] = {
64 0x00000000, 0x00502c38, /* Q1_1 */
65 0x00000004, 0x00102c38,
66 0x00000008, 0x00502c38,
67 0x0000000c, 0x00502c38,
68 0x00000010, 0x00502c38,
69 0x00000014, 0x00502c38,
70 0x00000018, 0x00502c38,
71 0x0000001c, 0x00502c38,
72 0x00000020, 0x00502c38,
73 0x00000024, 0x00502c38,
74 0x00000028, 0x00502c38,
75 0x0000002c, 0x00502c38,
76 0x00000030, 0x00102c38, /* Q2_1 */
77 0x00000034, 0x00102c38,
78 0x00000038, 0x00502c38,
79 0x0000003c, 0x00502c38,
80 0x00000040, 0x00102c38,
81 0x00000044, 0x00102c38,
82 0x00000048, 0x00502c38,
83 0x0000004c, 0x00502c38,
84 0x00000050, 0x00102c38,
85 0x00000054, 0x00102c38,
86 0x00000058, 0x00502c38,
87 0x0000005c, 0x00502c38,
88 0x00000060, 0x00502c38, /* Q3_1 */
89 0x00000064, 0x00502c38,
90 0x00000068, 0x00102c38,
91 0x0000006c, 0x00502c38,
92 0x000000d0, 0x00502c38,
93 0x000000d4, 0x00502c38,
94 0x000000d8, 0x00542c38,
95 0x000000dc, 0x00542c38,
96 0x000000e0, 0x00502c38,
97 0x000000e4, 0x00502c38,
98 0x000000e8, 0x00102c38,
99 0x000000ec, 0x00502c38,
100 0x000000f0, 0x00502c38, /* Q4_1 */
101 0x000000f4, 0x00502c38,
102 0x000000f8, 0x00102c38,
103 0x000000fc, 0x00502c38,
104 0x00000100, 0x00502c38,
105 0x00000104, 0x00502c38,
106 0x00000108, 0x00102c38,
107 0x0000010c, 0x00502c38,
108 0x00000110, 0x00502c38,
109 0x00000114, 0x00502c38,
110 0x00000118, 0x00542c38,
111 0x0000011c, 0x00102c38
112 };
113
114 const uint32_t sysmgr_pinmux_array_fpga[] = {
115 0x00000000, 0x00000000,
116 0x00000004, 0x00000000,
117 0x00000008, 0x00000000,
118 0x0000000c, 0x00000000,
119 0x00000010, 0x00000000,
120 0x00000014, 0x00000000,
121 0x00000018, 0x00000000,
122 0x0000001c, 0x00000000,
123 0x00000020, 0x00000000,
124 0x00000028, 0x00000000,
125 0x0000002c, 0x00000000,
126 0x00000030, 0x00000000,
127 0x00000034, 0x00000000,
128 0x00000038, 0x00000000,
129 0x0000003c, 0x00000000,
130 0x00000040, 0x00000000,
131 0x00000044, 0x00000000,
132 0x00000048, 0x00000000,
133 0x00000050, 0x00000000,
134 0x00000054, 0x00000000,
135 0x00000058, 0x0000002a
136 };
137
138 const uint32_t sysmgr_pinmux_array_iodelay[] = {
139 0x00000000, 0x00000000,
140 0x00000004, 0x00000000,
141 0x00000008, 0x00000000,
142 0x0000000c, 0x00000000,
143 0x00000010, 0x00000000,
144 0x00000014, 0x00000000,
145 0x00000018, 0x00000000,
146 0x0000001c, 0x00000000,
147 0x00000020, 0x00000000,
148 0x00000024, 0x00000000,
149 0x00000028, 0x00000000,
150 0x0000002c, 0x00000000,
151 0x00000030, 0x00000000,
152 0x00000034, 0x00000000,
153 0x00000038, 0x00000000,
154 0x0000003c, 0x00000000,
155 0x00000040, 0x00000000,
156 0x00000044, 0x00000000,
157 0x00000048, 0x00000000,
158 0x0000004c, 0x00000000,
159 0x00000050, 0x00000000,
160 0x00000054, 0x00000000,
161 0x00000058, 0x00000000,
162 0x0000005c, 0x00000000,
163 0x00000060, 0x00000000,
164 0x00000064, 0x00000000,
165 0x00000068, 0x00000000,
166 0x0000006c, 0x00000000,
167 0x00000070, 0x00000000,
168 0x00000074, 0x00000000,
169 0x00000078, 0x00000000,
170 0x0000007c, 0x00000000,
171 0x00000080, 0x00000000,
172 0x00000084, 0x00000000,
173 0x00000088, 0x00000000,
174 0x0000008c, 0x00000000,
175 0x00000090, 0x00000000,
176 0x00000094, 0x00000000,
177 0x00000098, 0x00000000,
178 0x0000009c, 0x00000000,
179 0x00000100, 0x00000000,
180 0x00000104, 0x00000000,
181 0x00000108, 0x00000000,
182 0x0000010c, 0x00000000,
183 0x00000110, 0x00000000,
184 0x00000114, 0x00000000,
185 0x00000118, 0x00000000,
186 0x0000011c, 0x00000000
187 };
188
config_fpgaintf_mod(void)189 void config_fpgaintf_mod(void)
190 {
191 uint32_t val;
192
193 val = 0;
194 if (mmio_read_32(AGX_PINMUX_NAND_USEFPGA) & 1)
195 val |= AGX_PINMUX_NAND_USEFPGA_VAL;
196 if (mmio_read_32(AGX_PINMUX_SDMMC_USEFPGA) & 1)
197 val |= AGX_PINMUX_SDMMC_USEFPGA_VAL;
198 if (mmio_read_32(AGX_PINMUX_SPIM0_USEFPGA) & 1)
199 val |= AGX_PINMUX_SPIM0_USEFPGA_VAL;
200 if (mmio_read_32(AGX_PINMUX_SPIM1_USEFPGA) & 1)
201 val |= AGX_PINMUX_SPIM1_USEFPGA_VAL;
202 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val);
203
204 val = 0;
205 if (mmio_read_32(AGX_PINMUX_EMAC0_USEFPGA) & 1)
206 val |= AGX_PINMUX_EMAC0_USEFPGA_VAL;
207 if (mmio_read_32(AGX_PINMUX_EMAC1_USEFPGA) & 1)
208 val |= AGX_PINMUX_EMAC1_USEFPGA_VAL;
209 if (mmio_read_32(AGX_PINMUX_EMAC2_USEFPGA) & 1)
210 val |= AGX_PINMUX_EMAC2_USEFPGA_VAL;
211 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), val);
212 }
213
214
config_pinmux(handoff * hoff_ptr)215 void config_pinmux(handoff *hoff_ptr)
216 {
217 unsigned int i;
218
219 for (i = 0; i < 96; i += 2) {
220 mmio_write_32(AGX_PINMUX_PIN0SEL +
221 hoff_ptr->pinmux_sel_array[i],
222 hoff_ptr->pinmux_sel_array[i+1]);
223 }
224
225 for (i = 0; i < 96; i += 2) {
226 mmio_write_32(AGX_PINMUX_IO0CTRL +
227 hoff_ptr->pinmux_io_array[i],
228 hoff_ptr->pinmux_io_array[i+1]);
229 }
230
231 for (i = 0; i < 40; i += 2) {
232 mmio_write_32(AGX_PINMUX_EMAC0_USEFPGA +
233 hoff_ptr->pinmux_fpga_array[i],
234 hoff_ptr->pinmux_fpga_array[i+1]);
235 }
236
237 for (i = 0; i < 96; i += 2) {
238 mmio_write_32(AGX_PINMUX_IO0_DELAY +
239 hoff_ptr->pinmux_iodelay_array[i],
240 hoff_ptr->pinmux_iodelay_array[i+1]);
241 }
242
243 config_fpgaintf_mod();
244 }
245
246
