1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/spinlock.h> 17 #include <lib/utils_def.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 20 /******************************************************************************* 21 * Forward declarations 22 ******************************************************************************/ 23 struct meminfo; 24 struct image_info; 25 struct bl_params; 26 27 typedef struct arm_tzc_regions_info { 28 unsigned long long base; 29 unsigned long long end; 30 unsigned int sec_attr; 31 unsigned int nsaid_permissions; 32 } arm_tzc_regions_info_t; 33 34 /******************************************************************************* 35 * Default mapping definition of the TrustZone Controller for ARM standard 36 * platforms. 37 * Configure: 38 * - Region 0 with no access; 39 * - Region 1 with secure access only; 40 * - the remaining DRAM regions access from the given Non-Secure masters. 41 ******************************************************************************/ 42 #if SPM_MM 43 #define ARM_TZC_REGIONS_DEF \ 44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 45 TZC_REGION_S_RDWR, 0}, \ 46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 50 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 52 PLAT_ARM_TZC_NS_DEV_ACCESS} 53 54 #elif ENABLE_RME 55 #define ARM_TZC_REGIONS_DEF \ 56 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 57 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 60 /* Realm and Shared area share the same PAS */ \ 61 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 64 PLAT_ARM_TZC_NS_DEV_ACCESS} 65 66 #else 67 #define ARM_TZC_REGIONS_DEF \ 68 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 69 TZC_REGION_S_RDWR, 0}, \ 70 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 71 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 72 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 73 PLAT_ARM_TZC_NS_DEV_ACCESS} 74 #endif 75 76 #define ARM_CASSERT_MMAP \ 77 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 78 assert_plat_arm_mmap_mismatch); \ 79 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 80 <= MAX_MMAP_REGIONS, \ 81 assert_max_mmap_regions); 82 83 void arm_setup_romlib(void); 84 85 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 86 /* 87 * Use this macro to instantiate lock before it is used in below 88 * arm_lock_xxx() macros 89 */ 90 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 91 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 92 93 #if !HW_ASSISTED_COHERENCY 94 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 95 #else 96 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 97 #endif 98 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 99 100 /* 101 * These are wrapper macros to the Coherent Memory Bakery Lock API. 102 */ 103 #define arm_lock_init() bakery_lock_init(&arm_lock) 104 #define arm_lock_get() bakery_lock_get(&arm_lock) 105 #define arm_lock_release() bakery_lock_release(&arm_lock) 106 107 #else 108 109 /* 110 * Empty macros for all other BL stages other than BL31 and BL32 111 */ 112 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 113 #define ARM_LOCK_GET_INSTANCE 0 114 #define arm_lock_init() 115 #define arm_lock_get() 116 #define arm_lock_release() 117 118 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 119 120 #if ARM_RECOM_STATE_ID_ENC 121 /* 122 * Macros used to parse state information from State-ID if it is using the 123 * recommended encoding for State-ID. 124 */ 125 #define ARM_LOCAL_PSTATE_WIDTH 4 126 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 127 128 /* Macros to construct the composite power state */ 129 130 /* Make composite power state parameter till power level 0 */ 131 #if PSCI_EXTENDED_STATE_ID 132 133 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 134 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 135 #else 136 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 137 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 138 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 139 ((type) << PSTATE_TYPE_SHIFT)) 140 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 141 142 /* Make composite power state parameter till power level 1 */ 143 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 144 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 145 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 146 147 /* Make composite power state parameter till power level 2 */ 148 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 149 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 150 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 151 152 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 153 154 /* ARM State switch error codes */ 155 #define STATE_SW_E_PARAM (-2) 156 #define STATE_SW_E_DENIED (-3) 157 158 /* plat_get_rotpk_info() flags */ 159 #define ARM_ROTPK_REGS_ID 1 160 #define ARM_ROTPK_DEVEL_RSA_ID 2 161 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 162 163 164 /* IO storage utility functions */ 165 int arm_io_setup(void); 166 167 /* Set image specification in IO block policy */ 168 int arm_set_image_source(unsigned int image_id, const char *part_name, 169 uintptr_t *dev_handle, uintptr_t *image_spec); 170 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 171 172 /* Security utility functions */ 173 void arm_tzc400_setup(uintptr_t tzc_base, 174 const arm_tzc_regions_info_t *tzc_regions); 175 struct tzc_dmc500_driver_data; 176 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 177 const arm_tzc_regions_info_t *tzc_regions); 178 179 /* Console utility functions */ 180 void arm_console_boot_init(void); 181 void arm_console_boot_end(void); 182 void arm_console_runtime_init(void); 183 void arm_console_runtime_end(void); 184 185 /* Systimer utility function */ 186 void arm_configure_sys_timer(void); 187 188 /* PM utility functions */ 189 int arm_validate_power_state(unsigned int power_state, 190 psci_power_state_t *req_state); 191 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 192 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 193 void arm_system_pwr_domain_save(void); 194 void arm_system_pwr_domain_resume(void); 195 int arm_psci_read_mem_protect(int *enabled); 196 int arm_nor_psci_write_mem_protect(int val); 197 void arm_nor_psci_do_static_mem_protect(void); 198 void arm_nor_psci_do_dyn_mem_protect(void); 199 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 200 201 /* Topology utility function */ 202 int arm_check_mpidr(u_register_t mpidr); 203 204 /* BL1 utility functions */ 205 void arm_bl1_early_platform_setup(void); 206 void arm_bl1_platform_setup(void); 207 void arm_bl1_plat_arch_setup(void); 208 209 /* BL2 utility functions */ 210 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 211 void arm_bl2_platform_setup(void); 212 void arm_bl2_plat_arch_setup(void); 213 uint32_t arm_get_spsr_for_bl32_entry(void); 214 uint32_t arm_get_spsr_for_bl33_entry(void); 215 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 216 int arm_bl2_handle_post_image_load(unsigned int image_id); 217 struct bl_params *arm_get_next_bl_params(void); 218 219 /* BL2 at EL3 functions */ 220 void arm_bl2_el3_early_platform_setup(void); 221 void arm_bl2_el3_plat_arch_setup(void); 222 223 /* BL2U utility functions */ 224 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 225 void *plat_info); 226 void arm_bl2u_platform_setup(void); 227 void arm_bl2u_plat_arch_setup(void); 228 229 /* BL31 utility functions */ 230 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 231 uintptr_t hw_config, void *plat_params_from_bl2); 232 void arm_bl31_platform_setup(void); 233 void arm_bl31_plat_runtime_setup(void); 234 void arm_bl31_plat_arch_setup(void); 235 236 /* TSP utility functions */ 237 void arm_tsp_early_platform_setup(void); 238 239 /* SP_MIN utility functions */ 240 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 241 uintptr_t hw_config, void *plat_params_from_bl2); 242 void arm_sp_min_plat_runtime_setup(void); 243 void arm_sp_min_plat_arch_setup(void); 244 245 /* FIP TOC validity check */ 246 bool arm_io_is_toc_valid(void); 247 248 /* Utility functions for Dynamic Config */ 249 void arm_bl2_dyn_cfg_init(void); 250 void arm_bl1_set_mbedtls_heap(void); 251 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 252 253 #if MEASURED_BOOT 254 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 255 int arm_set_nt_fw_info( 256 /* 257 * Currently OP-TEE does not support reading DTBs from Secure memory 258 * and this option should be removed when feature is supported. 259 */ 260 #ifdef SPD_opteed 261 uintptr_t log_addr, 262 #endif 263 size_t log_size, uintptr_t *ns_log_addr); 264 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size); 265 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size); 266 #endif /* MEASURED_BOOT */ 267 268 /* 269 * Free the memory storing initialization code only used during an images boot 270 * time so it can be reclaimed for runtime data 271 */ 272 void arm_free_init_memory(void); 273 274 /* 275 * Make the higher level translation tables read-only 276 */ 277 void arm_xlat_make_tables_readonly(void); 278 279 /* 280 * Mandatory functions required in ARM standard platforms 281 */ 282 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 283 void plat_arm_gic_driver_init(void); 284 void plat_arm_gic_init(void); 285 void plat_arm_gic_cpuif_enable(void); 286 void plat_arm_gic_cpuif_disable(void); 287 void plat_arm_gic_redistif_on(void); 288 void plat_arm_gic_redistif_off(void); 289 void plat_arm_gic_pcpu_init(void); 290 void plat_arm_gic_save(void); 291 void plat_arm_gic_resume(void); 292 void plat_arm_security_setup(void); 293 void plat_arm_pwrc_setup(void); 294 void plat_arm_interconnect_init(void); 295 void plat_arm_interconnect_enter_coherency(void); 296 void plat_arm_interconnect_exit_coherency(void); 297 void plat_arm_program_trusted_mailbox(uintptr_t address); 298 bool plat_arm_bl1_fwu_needed(void); 299 __dead2 void plat_arm_error_handler(int err); 300 301 /* 302 * Optional functions in ARM standard platforms 303 */ 304 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 305 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 306 unsigned int *flags); 307 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 308 unsigned int *flags); 309 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 310 unsigned int *flags); 311 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 312 unsigned int *flags); 313 314 #if ARM_PLAT_MT 315 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 316 #endif 317 318 /* 319 * This function is called after loading SCP_BL2 image and it is used to perform 320 * any platform-specific actions required to handle the SCP firmware. 321 */ 322 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 323 324 /* 325 * Optional functions required in ARM standard platforms 326 */ 327 void plat_arm_io_setup(void); 328 int plat_arm_get_alt_image_source( 329 unsigned int image_id, 330 uintptr_t *dev_handle, 331 uintptr_t *image_spec); 332 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 333 const mmap_region_t *plat_arm_get_mmap(void); 334 335 /* Allow platform to override psci_pm_ops during runtime */ 336 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 337 338 /* Execution state switch in ARM platforms */ 339 int arm_execution_state_switch(unsigned int smc_fid, 340 uint32_t pc_hi, 341 uint32_t pc_lo, 342 uint32_t cookie_hi, 343 uint32_t cookie_lo, 344 void *handle); 345 346 /* Optional functions for SP_MIN */ 347 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 348 u_register_t arg2, u_register_t arg3); 349 350 /* global variables */ 351 extern plat_psci_ops_t plat_arm_psci_pm_ops; 352 extern const mmap_region_t plat_arm_mmap[]; 353 extern const unsigned int arm_pm_idle_states[]; 354 355 /* secure watchdog */ 356 void plat_arm_secure_wdt_start(void); 357 void plat_arm_secure_wdt_stop(void); 358 359 /* Get SOC-ID of ARM platform */ 360 uint32_t plat_arm_get_soc_id(void); 361 362 #endif /* PLAT_ARM_H */ 363
