1 /*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch_features.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/arm/gicv3.h>
13 #include <drivers/arm/fvp/fvp_pwrc.h>
14 #include <lib/extensions/spe.h>
15 #include <lib/mmio.h>
16 #include <lib/psci/psci.h>
17 #include <plat/arm/common/arm_config.h>
18 #include <plat/arm/common/plat_arm.h>
19 #include <platform_def.h>
20
21 #include "fvp_private.h"
22 #include "../drivers/arm/gic/v3/gicv3_private.h"
23
24
25 #if ARM_RECOM_STATE_ID_ENC
26 /*
27 * The table storing the valid idle power states. Ensure that the
28 * array entries are populated in ascending order of state-id to
29 * enable us to use binary search during power state validation.
30 * The table must be terminated by a NULL entry.
31 */
32 const unsigned int arm_pm_idle_states[] = {
33 /* State-id - 0x01 */
34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
35 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
36 /* State-id - 0x02 */
37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
38 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
39 /* State-id - 0x22 */
40 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
41 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
42 /* State-id - 0x222 */
43 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
44 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
45 0,
46 };
47 #endif
48
49 /*******************************************************************************
50 * Function which implements the common FVP specific operations to power down a
51 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
52 ******************************************************************************/
fvp_cluster_pwrdwn_common(void)53 static void fvp_cluster_pwrdwn_common(void)
54 {
55 uint64_t mpidr = read_mpidr_el1();
56
57 /*
58 * On power down we need to disable statistical profiling extensions
59 * before exiting coherency.
60 */
61 if (is_feat_spe_supported()) {
62 spe_disable();
63 }
64
65 /* Disable coherency if this cluster is to be turned off */
66 fvp_interconnect_disable();
67
68 /* Program the power controller to turn the cluster off */
69 fvp_pwrc_write_pcoffr(mpidr);
70 }
71
72 /*
73 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
74 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
75 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
76 * from `fake` system suspend the GIC must not be powered off.
77 */
arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)78 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
79 {}
80
arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)81 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
82 {}
83
fvp_power_domain_on_finish_common(const psci_power_state_t * target_state)84 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
85 {
86 unsigned long mpidr;
87
88 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
89 ARM_LOCAL_STATE_OFF);
90
91 /* Get the mpidr for this cpu */
92 mpidr = read_mpidr_el1();
93
94 /* Perform the common cluster specific operations */
95 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
96 ARM_LOCAL_STATE_OFF) {
97 /*
98 * This CPU might have woken up whilst the cluster was
99 * attempting to power down. In this case the FVP power
100 * controller will have a pending cluster power off request
101 * which needs to be cleared by writing to the PPONR register.
102 * This prevents the power controller from interpreting a
103 * subsequent entry of this cpu into a simple wfi as a power
104 * down request.
105 */
106 fvp_pwrc_write_pponr(mpidr);
107
108 /* Enable coherency if this cluster was off */
109 fvp_interconnect_enable();
110 }
111 /* Perform the common system specific operations */
112 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
113 ARM_LOCAL_STATE_OFF)
114 arm_system_pwr_domain_resume();
115
116 /*
117 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
118 * with a cpu power down unless the bit is set again
119 */
120 fvp_pwrc_clr_wen(mpidr);
121 }
122
123 /*******************************************************************************
124 * FVP handler called when a CPU is about to enter standby.
125 ******************************************************************************/
fvp_cpu_standby(plat_local_state_t cpu_state)126 static void fvp_cpu_standby(plat_local_state_t cpu_state)
127 {
128 u_register_t scr = read_scr_el3();
129
130 assert(cpu_state == ARM_LOCAL_STATE_RET);
131
132 /*
133 * Enable the Non-secure interrupt to wake the CPU.
134 * In GICv3 affinity routing mode, the Non-secure Group 1 interrupts
135 * use Physical FIQ at EL3 whereas in GICv2, Physical IRQ is used.
136 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
137 * routing mode.
138 */
139 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
140 isb();
141
142 /*
143 * Enter standby state.
144 * dsb is good practice before using wfi to enter low power states.
145 */
146 dsb();
147 wfi();
148
149 /*
150 * Restore SCR_EL3 to the original value, synchronisation of SCR_EL3
151 * is done by eret in el3_exit() to save some execution cycles.
152 */
153 write_scr_el3(scr);
154 }
155
156 /*******************************************************************************
157 * FVP handler called when a power domain is about to be turned on. The
158 * mpidr determines the CPU to be turned on.
159 ******************************************************************************/
fvp_pwr_domain_on(u_register_t mpidr)160 static int fvp_pwr_domain_on(u_register_t mpidr)
161 {
162 int rc = PSCI_E_SUCCESS;
163 unsigned int psysr;
164
165 /*
166 * Ensure that we do not cancel an inflight power off request for the
167 * target cpu. That would leave it in a zombie wfi. Wait for it to power
168 * off and then program the power controller to turn that CPU on.
169 */
170 do {
171 psysr = fvp_pwrc_read_psysr(mpidr);
172 } while ((psysr & PSYSR_AFF_L0) != 0U);
173
174 fvp_pwrc_write_pponr(mpidr);
175 return rc;
176 }
177
178 /*******************************************************************************
179 * FVP handler called when a power domain is about to be turned off. The
180 * target_state encodes the power state that each level should transition to.
181 ******************************************************************************/
fvp_pwr_domain_off(const psci_power_state_t * target_state)182 static void fvp_pwr_domain_off(const psci_power_state_t *target_state)
183 {
184 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
185 ARM_LOCAL_STATE_OFF);
186
187 /*
188 * If execution reaches this stage then this power domain will be
189 * suspended. Perform at least the cpu specific actions followed
190 * by the cluster specific operations if applicable.
191 */
192
193 /* Prevent interrupts from spuriously waking up this cpu */
194 plat_arm_gic_cpuif_disable();
195
196 /* Turn redistributor off */
197 plat_arm_gic_redistif_off();
198
199 /* Program the power controller to power off this cpu. */
200 fvp_pwrc_write_ppoffr(read_mpidr_el1());
201
202 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
203 ARM_LOCAL_STATE_OFF)
204 fvp_cluster_pwrdwn_common();
205
206 }
207
208 /*******************************************************************************
209 * FVP handler called when a power domain is about to be suspended. The
210 * target_state encodes the power state that each level should transition to.
211 ******************************************************************************/
fvp_pwr_domain_suspend(const psci_power_state_t * target_state)212 static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
213 {
214 unsigned long mpidr;
215
216 /*
217 * FVP has retention only at cpu level. Just return
218 * as nothing is to be done for retention.
219 */
220 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
221 ARM_LOCAL_STATE_RET)
222 return;
223
224 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
225 ARM_LOCAL_STATE_OFF);
226
227 /* Get the mpidr for this cpu */
228 mpidr = read_mpidr_el1();
229
230 /* Program the power controller to enable wakeup interrupts. */
231 fvp_pwrc_set_wen(mpidr);
232
233 /* Prevent interrupts from spuriously waking up this cpu */
234 plat_arm_gic_cpuif_disable();
235
236 /*
237 * The Redistributor is not powered off as it can potentially prevent
238 * wake up events reaching the CPUIF and/or might lead to losing
239 * register context.
240 */
241
242 /* Perform the common cluster specific operations */
243 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
244 ARM_LOCAL_STATE_OFF)
245 fvp_cluster_pwrdwn_common();
246
247 /* Perform the common system specific operations */
248 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
249 ARM_LOCAL_STATE_OFF)
250 arm_system_pwr_domain_save();
251
252 /* Program the power controller to power off this cpu. */
253 fvp_pwrc_write_ppoffr(read_mpidr_el1());
254
255 return;
256 }
257
258 /*******************************************************************************
259 * FVP handler called when a power domain has just been powered on after
260 * being turned off earlier. The target_state encodes the low power state that
261 * each level has woken up from.
262 ******************************************************************************/
fvp_pwr_domain_on_finish(const psci_power_state_t * target_state)263 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
264 {
265 fvp_power_domain_on_finish_common(target_state);
266
267 }
268
269 /*******************************************************************************
270 * FVP handler called when a power domain has just been powered on and the cpu
271 * and its cluster are fully participating in coherent transaction on the
272 * interconnect. Data cache must be enabled for CPU at this point.
273 ******************************************************************************/
fvp_pwr_domain_on_finish_late(const psci_power_state_t * target_state)274 static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
275 {
276 /* Program GIC per-cpu distributor or re-distributor interface */
277 plat_arm_gic_pcpu_init();
278
279 /* Enable GIC CPU interface */
280 plat_arm_gic_cpuif_enable();
281 }
282
283 /*******************************************************************************
284 * FVP handler called when a power domain has just been powered on after
285 * having been suspended earlier. The target_state encodes the low power state
286 * that each level has woken up from.
287 * TODO: At the moment we reuse the on finisher and reinitialize the secure
288 * context. Need to implement a separate suspend finisher.
289 ******************************************************************************/
fvp_pwr_domain_suspend_finish(const psci_power_state_t * target_state)290 static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
291 {
292 /*
293 * Nothing to be done on waking up from retention from CPU level.
294 */
295 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
296 ARM_LOCAL_STATE_RET)
297 return;
298
299 fvp_power_domain_on_finish_common(target_state);
300
301 /* Enable GIC CPU interface */
302 plat_arm_gic_cpuif_enable();
303 }
304
305 /*******************************************************************************
306 * FVP handlers to shutdown/reboot the system
307 ******************************************************************************/
fvp_system_off(void)308 static void __dead2 fvp_system_off(void)
309 {
310 /* Write the System Configuration Control Register */
311 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
312 V2M_CFGCTRL_START |
313 V2M_CFGCTRL_RW |
314 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
315 wfi();
316 ERROR("FVP System Off: operation not handled.\n");
317 panic();
318 }
319
fvp_system_reset(void)320 static void __dead2 fvp_system_reset(void)
321 {
322 /* Write the System Configuration Control Register */
323 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
324 V2M_CFGCTRL_START |
325 V2M_CFGCTRL_RW |
326 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
327 wfi();
328 ERROR("FVP System Reset: operation not handled.\n");
329 panic();
330 }
331
fvp_node_hw_state(u_register_t target_cpu,unsigned int power_level)332 static int fvp_node_hw_state(u_register_t target_cpu,
333 unsigned int power_level)
334 {
335 unsigned int psysr;
336 int ret;
337
338 /*
339 * The format of 'power_level' is implementation-defined, but 0 must
340 * mean a CPU. We also allow 1 to denote the cluster
341 */
342 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1))
343 return PSCI_E_INVALID_PARAMS;
344
345 /*
346 * Read the status of the given MPDIR from FVP power controller. The
347 * power controller only gives us on/off status, so map that to expected
348 * return values of the PSCI call
349 */
350 psysr = fvp_pwrc_read_psysr(target_cpu);
351 if (psysr == PSYSR_INVALID)
352 return PSCI_E_INVALID_PARAMS;
353
354 if (power_level == ARM_PWR_LVL0) {
355 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF;
356 } else {
357 /* power_level == ARM_PWR_LVL1 */
358 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF;
359 }
360
361 return ret;
362 }
363
364 /*
365 * The FVP doesn't truly support power management at SYSTEM power domain. The
366 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
367 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
368 * save and restore sequences on FVP.
369 */
370 #if !ARM_BL31_IN_DRAM
fvp_get_sys_suspend_power_state(psci_power_state_t * req_state)371 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
372 {
373 unsigned int i;
374
375 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
376 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
377
378 #if PSCI_OS_INIT_MODE
379 req_state->last_at_pwrlvl = PLAT_MAX_PWR_LVL;
380 #endif
381 }
382 #endif
383
384 /*******************************************************************************
385 * Handler to filter PSCI requests.
386 ******************************************************************************/
387 /*
388 * The system power domain suspend is only supported only via
389 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
390 * will be downgraded to the lower level.
391 */
fvp_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)392 static int fvp_validate_power_state(unsigned int power_state,
393 psci_power_state_t *req_state)
394 {
395 int rc;
396 rc = arm_validate_power_state(power_state, req_state);
397
398 /*
399 * Ensure that the system power domain level is never suspended
400 * via PSCI CPU SUSPEND API. Currently system suspend is only
401 * supported via PSCI SYSTEM SUSPEND API.
402 */
403 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
404 return rc;
405 }
406
407 /*
408 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
409 * `fvp_validate_power_state`, we do not downgrade the system power
410 * domain level request in `power_state` as it will be used to query the
411 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
412 */
fvp_translate_power_state_by_mpidr(u_register_t mpidr,unsigned int power_state,psci_power_state_t * output_state)413 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
414 unsigned int power_state,
415 psci_power_state_t *output_state)
416 {
417 return arm_validate_power_state(power_state, output_state);
418 }
419
420 /*******************************************************************************
421 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
422 * platform layer will take care of registering the handlers with PSCI.
423 ******************************************************************************/
424 plat_psci_ops_t plat_arm_psci_pm_ops = {
425 .cpu_standby = fvp_cpu_standby,
426 .pwr_domain_on = fvp_pwr_domain_on,
427 .pwr_domain_off = fvp_pwr_domain_off,
428 .pwr_domain_suspend = fvp_pwr_domain_suspend,
429 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
430 .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late,
431 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
432 .system_off = fvp_system_off,
433 .system_reset = fvp_system_reset,
434 .validate_power_state = fvp_validate_power_state,
435 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
436 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
437 .get_node_hw_state = fvp_node_hw_state,
438 #if !ARM_BL31_IN_DRAM
439 /*
440 * The TrustZone Controller is set up during the warmboot sequence after
441 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM
442 * this is not a problem but, if it is in TZC-secured DRAM, it tries to
443 * reconfigure the same memory it is running on, causing an exception.
444 */
445 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
446 #endif
447 .mem_protect_chk = arm_psci_mem_protect_chk,
448 .read_mem_protect = arm_psci_read_mem_protect,
449 .write_mem_protect = arm_nor_psci_write_mem_protect,
450 };
451
plat_arm_psci_override_pm_ops(plat_psci_ops_t * ops)452 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
453 {
454 return ops;
455 }
456
