1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMV71J19B 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:20:53Z */ 31 #ifndef _SAMV71J19B_PIO_H_ 32 #define _SAMV71J19B_PIO_H_ 33 34 /* ========== Peripheral I/O pin numbers ========== */ 35 #define PIN_PA0 ( 0) /**< Pin Number for PA0 */ 36 #define PIN_PA1 ( 1) /**< Pin Number for PA1 */ 37 #define PIN_PA2 ( 2) /**< Pin Number for PA2 */ 38 #define PIN_PA3 ( 3) /**< Pin Number for PA3 */ 39 #define PIN_PA4 ( 4) /**< Pin Number for PA4 */ 40 #define PIN_PA5 ( 5) /**< Pin Number for PA5 */ 41 #define PIN_PA6 ( 6) /**< Pin Number for PA6 */ 42 #define PIN_PA7 ( 7) /**< Pin Number for PA7 */ 43 #define PIN_PA8 ( 8) /**< Pin Number for PA8 */ 44 #define PIN_PA9 ( 9) /**< Pin Number for PA9 */ 45 #define PIN_PA10 ( 10) /**< Pin Number for PA10 */ 46 #define PIN_PA11 ( 11) /**< Pin Number for PA11 */ 47 #define PIN_PA12 ( 12) /**< Pin Number for PA12 */ 48 #define PIN_PA13 ( 13) /**< Pin Number for PA13 */ 49 #define PIN_PA14 ( 14) /**< Pin Number for PA14 */ 50 #define PIN_PA15 ( 15) /**< Pin Number for PA15 */ 51 #define PIN_PA16 ( 16) /**< Pin Number for PA16 */ 52 #define PIN_PA17 ( 17) /**< Pin Number for PA17 */ 53 #define PIN_PA18 ( 18) /**< Pin Number for PA18 */ 54 #define PIN_PA19 ( 19) /**< Pin Number for PA19 */ 55 #define PIN_PA20 ( 20) /**< Pin Number for PA20 */ 56 #define PIN_PA21 ( 21) /**< Pin Number for PA21 */ 57 #define PIN_PA22 ( 22) /**< Pin Number for PA22 */ 58 #define PIN_PA23 ( 23) /**< Pin Number for PA23 */ 59 #define PIN_PA24 ( 24) /**< Pin Number for PA24 */ 60 #define PIN_PA25 ( 25) /**< Pin Number for PA25 */ 61 #define PIN_PA26 ( 26) /**< Pin Number for PA26 */ 62 #define PIN_PA27 ( 27) /**< Pin Number for PA27 */ 63 #define PIN_PA28 ( 28) /**< Pin Number for PA28 */ 64 #define PIN_PA29 ( 29) /**< Pin Number for PA29 */ 65 #define PIN_PA30 ( 30) /**< Pin Number for PA30 */ 66 #define PIN_PA31 ( 31) /**< Pin Number for PA31 */ 67 #define PIN_PB0 ( 32) /**< Pin Number for PB0 */ 68 #define PIN_PB1 ( 33) /**< Pin Number for PB1 */ 69 #define PIN_PB2 ( 34) /**< Pin Number for PB2 */ 70 #define PIN_PB3 ( 35) /**< Pin Number for PB3 */ 71 #define PIN_PB4 ( 36) /**< Pin Number for PB4 */ 72 #define PIN_PB5 ( 37) /**< Pin Number for PB5 */ 73 #define PIN_PB6 ( 38) /**< Pin Number for PB6 */ 74 #define PIN_PB7 ( 39) /**< Pin Number for PB7 */ 75 #define PIN_PB8 ( 40) /**< Pin Number for PB8 */ 76 #define PIN_PB9 ( 41) /**< Pin Number for PB9 */ 77 #define PIN_PB12 ( 44) /**< Pin Number for PB12 */ 78 #define PIN_PB13 ( 45) /**< Pin Number for PB13 */ 79 #define PIN_PD0 ( 96) /**< Pin Number for PD0 */ 80 #define PIN_PD1 ( 97) /**< Pin Number for PD1 */ 81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */ 82 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */ 83 #define PIN_PD4 (100) /**< Pin Number for PD4 */ 84 #define PIN_PD5 (101) /**< Pin Number for PD5 */ 85 #define PIN_PD6 (102) /**< Pin Number for PD6 */ 86 #define PIN_PD7 (103) /**< Pin Number for PD7 */ 87 #define PIN_PD8 (104) /**< Pin Number for PD8 */ 88 #define PIN_PD9 (105) /**< Pin Number for PD9 */ 89 #define PIN_PD10 (106) /**< Pin Number for PD10 */ 90 #define PIN_PD11 (107) /**< Pin Number for PD11 */ 91 #define PIN_PD12 (108) /**< Pin Number for PD12 */ 92 #define PIN_PD13 (109) /**< Pin Number for PD13 */ 93 #define PIN_PD14 (110) /**< Pin Number for PD14 */ 94 #define PIN_PD15 (111) /**< Pin Number for PD15 */ 95 #define PIN_PD16 (112) /**< Pin Number for PD16 */ 96 #define PIN_PD17 (113) /**< Pin Number for PD17 */ 97 #define PIN_PD18 (114) /**< Pin Number for PD18 */ 98 #define PIN_PD19 (115) /**< Pin Number for PD19 */ 99 #define PIN_PD20 (116) /**< Pin Number for PD20 */ 100 #define PIN_PD21 (117) /**< Pin Number for PD21 */ 101 #define PIN_PD22 (118) /**< Pin Number for PD22 */ 102 #define PIN_PD23 (119) /**< Pin Number for PD23 */ 103 #define PIN_PD24 (120) /**< Pin Number for PD24 */ 104 #define PIN_PD25 (121) /**< Pin Number for PD25 */ 105 #define PIN_PD26 (122) /**< Pin Number for PD26 */ 106 #define PIN_PD27 (123) /**< Pin Number for PD27 */ 107 #define PIN_PD28 (124) /**< Pin Number for PD28 */ 108 #define PIN_PD29 (125) /**< Pin Number for PD29 */ 109 #define PIN_PD30 (126) /**< Pin Number for PD30 */ 110 #define PIN_PD31 (127) /**< Pin Number for PD31 */ 111 112 113 /* ========== Peripheral I/O masks ========== */ 114 #define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ 115 #define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ 116 #define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ 117 #define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ 118 #define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ 119 #define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ 120 #define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ 121 #define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ 122 #define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ 123 #define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ 124 #define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ 125 #define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ 126 #define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ 127 #define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ 128 #define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ 129 #define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ 130 #define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ 131 #define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ 132 #define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ 133 #define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ 134 #define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ 135 #define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ 136 #define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ 137 #define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ 138 #define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ 139 #define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ 140 #define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ 141 #define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ 142 #define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ 143 #define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ 144 #define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ 145 #define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ 146 #define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ 147 #define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ 148 #define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ 149 #define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ 150 #define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ 151 #define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ 152 #define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ 153 #define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ 154 #define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ 155 #define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ 156 #define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ 157 #define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ 158 #define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ 159 #define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ 160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ 161 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ 162 #define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ 163 #define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ 164 #define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ 165 #define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ 166 #define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ 167 #define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ 168 #define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ 169 #define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ 170 #define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ 171 #define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ 172 #define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ 173 #define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ 174 #define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ 175 #define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ 176 #define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ 177 #define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ 178 #define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ 179 #define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ 180 #define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ 181 #define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ 182 #define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ 183 #define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ 184 #define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ 185 #define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ 186 #define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ 187 #define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ 188 #define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ 189 #define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ 190 191 192 /* ========== Peripheral I/O indexes ========== */ 193 #define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ 194 #define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ 195 #define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ 196 #define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ 197 #define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ 198 #define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ 199 #define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ 200 #define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ 201 #define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ 202 #define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ 203 #define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ 204 #define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ 205 #define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ 206 #define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ 207 #define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ 208 #define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ 209 #define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ 210 #define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ 211 #define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ 212 #define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ 213 #define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ 214 #define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ 215 #define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ 216 #define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ 217 #define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ 218 #define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ 219 #define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ 220 #define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ 221 #define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ 222 #define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ 223 #define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ 224 #define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ 225 #define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ 226 #define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ 227 #define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ 228 #define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ 229 #define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ 230 #define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ 231 #define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ 232 #define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ 233 #define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ 234 #define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ 235 #define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ 236 #define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ 237 #define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ 238 #define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ 239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ 240 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ 241 #define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ 242 #define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ 243 #define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ 244 #define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ 245 #define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ 246 #define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ 247 #define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ 248 #define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ 249 #define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ 250 #define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ 251 #define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ 252 #define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ 253 #define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ 254 #define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ 255 #define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ 256 #define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ 257 #define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ 258 #define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ 259 #define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ 260 #define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ 261 #define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ 262 #define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ 263 #define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ 264 #define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ 265 #define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ 266 #define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ 267 #define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ 268 #define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ 269 270 /* ========== PIO definition for AFEC0 peripheral ========== */ 271 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ 272 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ 273 #define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) 274 275 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ 276 #define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) 277 278 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ 279 #define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) 280 281 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ 282 #define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) 283 284 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ 285 #define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) 286 287 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ 288 #define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) 289 290 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ 291 #define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) 292 293 #define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ 294 #define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) 295 296 #define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ 297 #define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) 298 299 #define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ 300 #define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) 301 302 /* ========== PIO definition for AFEC1 peripheral ========== */ 303 #define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ 304 #define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ 305 #define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) 306 307 #define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ 308 #define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) 309 310 /* ========== PIO definition for DACC peripheral ========== */ 311 #define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ 312 #define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) 313 314 #define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ 315 #define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) 316 317 #define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ 318 #define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ 319 #define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) 320 321 /* ========== PIO definition for EFC peripheral ========== */ 322 #define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ 323 #define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) 324 325 /* ========== PIO definition for GMAC peripheral ========== */ 326 #define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ 327 #define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ 328 #define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) 329 330 #define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ 331 #define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ 332 #define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) 333 334 #define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ 335 #define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ 336 #define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) 337 338 #define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ 339 #define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ 340 #define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) 341 342 #define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ 343 #define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ 344 #define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) 345 346 #define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ 347 #define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ 348 #define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) 349 350 #define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ 351 #define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ 352 #define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) 353 354 #define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ 355 #define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ 356 #define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) 357 358 #define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ 359 #define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ 360 #define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) 361 362 #define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ 363 #define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ 364 #define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) 365 366 #define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ 367 #define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ 368 #define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) 369 370 #define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ 371 #define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ 372 #define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) 373 374 #define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ 375 #define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ 376 #define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) 377 378 #define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ 379 #define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ 380 #define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) 381 382 #define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ 383 #define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ 384 #define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) 385 386 #define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ 387 #define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ 388 #define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) 389 390 #define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ 391 #define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ 392 #define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) 393 394 #define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ 395 #define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ 396 #define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) 397 398 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ 399 #define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ 400 #define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) 401 402 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ 403 #define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ 404 #define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) 405 406 #define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ 407 #define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ 408 #define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) 409 410 #define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ 411 #define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ 412 #define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) 413 414 /* ========== PIO definition for ISI peripheral ========== */ 415 #define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ 416 #define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ 417 #define PIO_PD22D_ISI_D0 (_UL_(1) << 22) 418 419 #define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ 420 #define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ 421 #define PIO_PD21D_ISI_D1 (_UL_(1) << 21) 422 423 #define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ 424 #define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ 425 #define PIO_PB3D_ISI_D2 (_UL_(1) << 3) 426 427 #define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ 428 #define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ 429 #define PIO_PA9B_ISI_D3 (_UL_(1) << 9) 430 431 #define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ 432 #define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ 433 #define PIO_PA5B_ISI_D4 (_UL_(1) << 5) 434 435 #define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ 436 #define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ 437 #define PIO_PD11D_ISI_D5 (_UL_(1) << 11) 438 439 #define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ 440 #define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ 441 #define PIO_PD12D_ISI_D6 (_UL_(1) << 12) 442 443 #define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ 444 #define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ 445 #define PIO_PA27D_ISI_D7 (_UL_(1) << 27) 446 447 #define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ 448 #define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ 449 #define PIO_PD27D_ISI_D8 (_UL_(1) << 27) 450 451 #define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ 452 #define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ 453 #define PIO_PD28D_ISI_D9 (_UL_(1) << 28) 454 455 #define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ 456 #define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ 457 #define PIO_PD30D_ISI_D10 (_UL_(1) << 30) 458 459 #define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ 460 #define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ 461 #define PIO_PD31D_ISI_D11 (_UL_(1) << 31) 462 463 #define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ 464 #define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ 465 #define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) 466 467 #define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ 468 #define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ 469 #define PIO_PA24D_ISI_PCK (_UL_(1) << 24) 470 471 #define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ 472 #define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ 473 #define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) 474 475 /* ========== PIO definition for MCAN0 peripheral ========== */ 476 #define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ 477 #define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ 478 #define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) 479 480 #define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ 481 #define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ 482 #define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) 483 484 /* ========== PIO definition for MLB peripheral ========== */ 485 #define PIN_PB4C_MLB_MLBCLK _L_(36) /**< MLB signal: MLBCLK on PB4 mux C*/ 486 #define MUX_PB4C_MLB_MLBCLK _L_(2) /**< MLB signal line function value: MLBCLK */ 487 #define PIO_PB4C_MLB_MLBCLK (_UL_(1) << 4) 488 489 #define PIN_PB5C_MLB_MLBDAT _L_(37) /**< MLB signal: MLBDAT on PB5 mux C*/ 490 #define MUX_PB5C_MLB_MLBDAT _L_(2) /**< MLB signal line function value: MLBDAT */ 491 #define PIO_PB5C_MLB_MLBDAT (_UL_(1) << 5) 492 493 #define PIN_PD10D_MLB_MLBSIG _L_(106) /**< MLB signal: MLBSIG on PD10 mux D*/ 494 #define MUX_PD10D_MLB_MLBSIG _L_(3) /**< MLB signal line function value: MLBSIG */ 495 #define PIO_PD10D_MLB_MLBSIG (_UL_(1) << 10) 496 497 /* ========== PIO definition for PMC peripheral ========== */ 498 #define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ 499 #define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ 500 #define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) 501 502 #define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ 503 #define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ 504 #define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) 505 506 #define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ 507 #define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ 508 #define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) 509 510 #define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ 511 #define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ 512 #define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) 513 514 #define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ 515 #define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ 516 #define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) 517 518 #define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ 519 #define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ 520 #define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) 521 522 #define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ 523 #define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 524 #define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) 525 526 #define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ 527 #define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 528 #define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) 529 530 #define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ 531 #define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 532 #define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) 533 534 #define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ 535 #define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ 536 #define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) 537 538 #define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ 539 #define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) 540 541 #define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ 542 #define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) 543 544 #define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ 545 #define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) 546 547 #define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ 548 #define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) 549 550 /* ========== PIO definition for PWM0 peripheral ========== */ 551 #define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ 552 #define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ 553 #define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) 554 555 #define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ 556 #define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ 557 #define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) 558 559 #define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ 560 #define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ 561 #define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) 562 563 #define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ 564 #define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ 565 #define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) 566 567 #define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ 568 #define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ 569 #define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) 570 571 #define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ 572 #define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 573 #define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) 574 575 #define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ 576 #define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 577 #define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) 578 579 #define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ 580 #define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 581 #define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) 582 583 #define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ 584 #define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 585 #define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) 586 587 #define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ 588 #define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 589 #define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) 590 591 #define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ 592 #define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 593 #define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) 594 595 #define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ 596 #define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 597 #define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) 598 599 #define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ 600 #define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ 601 #define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) 602 603 #define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ 604 #define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ 605 #define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) 606 607 #define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ 608 #define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 609 #define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) 610 611 #define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ 612 #define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 613 #define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) 614 615 #define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ 616 #define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 617 #define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) 618 619 #define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ 620 #define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 621 #define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) 622 623 #define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ 624 #define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 625 #define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) 626 627 #define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ 628 #define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ 629 #define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) 630 631 #define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ 632 #define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 633 #define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) 634 635 #define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ 636 #define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 637 #define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) 638 639 #define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ 640 #define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ 641 #define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) 642 643 #define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ 644 #define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ 645 #define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) 646 647 #define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ 648 #define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ 649 #define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) 650 651 #define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ 652 #define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 653 #define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) 654 655 #define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ 656 #define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 657 #define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) 658 659 #define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ 660 #define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 661 #define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) 662 663 #define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ 664 #define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ 665 #define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) 666 667 #define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ 668 #define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ 669 #define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) 670 671 #define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ 672 #define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ 673 #define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) 674 675 #define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ 676 #define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ 677 #define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) 678 679 #define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ 680 #define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ 681 #define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) 682 683 #define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ 684 #define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 685 #define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) 686 687 #define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ 688 #define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 689 #define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) 690 691 #define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ 692 #define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 693 #define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) 694 695 #define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ 696 #define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ 697 #define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) 698 699 #define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ 700 #define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ 701 #define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) 702 703 /* ========== PIO definition for PWM1 peripheral ========== */ 704 #define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ 705 #define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ 706 #define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) 707 708 #define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ 709 #define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ 710 #define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) 711 712 #define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ 713 #define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ 714 #define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) 715 716 #define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ 717 #define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ 718 #define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) 719 720 #define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ 721 #define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ 722 #define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) 723 724 #define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ 725 #define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ 726 #define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) 727 728 #define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ 729 #define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ 730 #define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) 731 732 #define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ 733 #define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ 734 #define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) 735 736 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ 737 #define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ 738 #define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) 739 740 #define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ 741 #define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ 742 #define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) 743 744 #define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ 745 #define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ 746 #define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) 747 748 #define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ 749 #define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ 750 #define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) 751 752 #define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ 753 #define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ 754 #define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) 755 756 #define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ 757 #define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ 758 #define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) 759 760 #define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ 761 #define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ 762 #define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) 763 764 #define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ 765 #define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ 766 #define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) 767 768 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ 769 #define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ 770 #define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) 771 772 #define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ 773 #define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ 774 #define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) 775 776 #define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ 777 #define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ 778 #define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) 779 780 #define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ 781 #define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ 782 #define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) 783 784 #define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ 785 #define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ 786 #define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) 787 788 /* ========== PIO definition for QSPI peripheral ========== */ 789 #define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ 790 #define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ 791 #define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) 792 793 #define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ 794 #define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ 795 #define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) 796 797 #define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ 798 #define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ 799 #define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) 800 801 #define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ 802 #define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ 803 #define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) 804 805 #define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ 806 #define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ 807 #define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) 808 809 #define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ 810 #define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ 811 #define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) 812 813 /* ========== PIO definition for RTC peripheral ========== */ 814 #define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ 815 #define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) 816 817 #define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ 818 #define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) 819 820 /* ========== PIO definition for SSC peripheral ========== */ 821 #define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ 822 #define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ 823 #define PIO_PA10C_SSC_RD (_UL_(1) << 10) 824 825 #define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ 826 #define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ 827 #define PIO_PD24B_SSC_RF (_UL_(1) << 24) 828 829 #define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ 830 #define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ 831 #define PIO_PA22A_SSC_RK (_UL_(1) << 22) 832 833 #define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ 834 #define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ 835 #define PIO_PB5D_SSC_TD (_UL_(1) << 5) 836 837 #define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ 838 #define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ 839 #define PIO_PD10C_SSC_TD (_UL_(1) << 10) 840 841 #define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ 842 #define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ 843 #define PIO_PD26B_SSC_TD (_UL_(1) << 26) 844 845 #define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ 846 #define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ 847 #define PIO_PB0D_SSC_TF (_UL_(1) << 0) 848 849 #define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ 850 #define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ 851 #define PIO_PB1D_SSC_TK (_UL_(1) << 1) 852 853 /* ========== PIO definition for SUPC peripheral ========== */ 854 #define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ 855 #define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) 856 857 #define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ 858 #define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) 859 860 #define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ 861 #define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) 862 863 #define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ 864 #define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) 865 866 #define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ 867 #define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) 868 869 #define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ 870 #define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) 871 872 #define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ 873 #define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) 874 875 #define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ 876 #define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) 877 878 #define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ 879 #define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) 880 881 #define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ 882 #define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) 883 884 #define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ 885 #define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) 886 887 #define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ 888 #define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) 889 890 #define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ 891 #define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) 892 893 #define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ 894 #define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) 895 896 /* ========== PIO definition for TC0 peripheral ========== */ 897 #define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ 898 #define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ 899 #define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) 900 901 #define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ 902 #define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ 903 #define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) 904 905 #define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ 906 #define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ 907 #define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) 908 909 #define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ 910 #define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ 911 #define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) 912 913 #define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ 914 #define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ 915 #define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) 916 917 #define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ 918 #define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ 919 #define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) 920 921 #define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ 922 #define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ 923 #define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) 924 925 #define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ 926 #define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ 927 #define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) 928 929 #define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ 930 #define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ 931 #define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) 932 933 /* ========== PIO definition for TC3 peripheral ========== */ 934 #define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ 935 #define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ 936 #define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) 937 938 #define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ 939 #define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ 940 #define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) 941 942 #define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ 943 #define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ 944 #define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) 945 946 /* ========== PIO definition for TWIHS0 peripheral ========== */ 947 #define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ 948 #define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ 949 #define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) 950 951 #define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ 952 #define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ 953 #define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) 954 955 /* ========== PIO definition for TWIHS1 peripheral ========== */ 956 #define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ 957 #define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ 958 #define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) 959 960 #define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ 961 #define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ 962 #define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) 963 964 /* ========== PIO definition for UART0 peripheral ========== */ 965 #define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ 966 #define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ 967 #define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) 968 969 #define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ 970 #define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ 971 #define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) 972 973 /* ========== PIO definition for UART1 peripheral ========== */ 974 #define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ 975 #define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ 976 #define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) 977 978 #define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ 979 #define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ 980 #define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) 981 982 #define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ 983 #define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ 984 #define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) 985 986 #define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ 987 #define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ 988 #define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) 989 990 /* ========== PIO definition for UART2 peripheral ========== */ 991 #define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ 992 #define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ 993 #define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) 994 995 #define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ 996 #define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ 997 #define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) 998 999 /* ========== PIO definition for USART0 peripheral ========== */ 1000 #define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ 1001 #define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ 1002 #define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) 1003 1004 #define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ 1005 #define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ 1006 #define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) 1007 1008 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ 1009 #define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ 1010 #define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) 1011 1012 #define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ 1013 #define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ 1014 #define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) 1015 1016 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ 1017 #define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ 1018 #define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) 1019 1020 #define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ 1021 #define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ 1022 #define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) 1023 1024 #define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ 1025 #define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ 1026 #define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) 1027 1028 #define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ 1029 #define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ 1030 #define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) 1031 1032 #define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ 1033 #define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ 1034 #define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) 1035 1036 /* ========== PIO definition for USART1 peripheral ========== */ 1037 #define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ 1038 #define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ 1039 #define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) 1040 1041 #define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ 1042 #define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ 1043 #define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) 1044 1045 #define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ 1046 #define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ 1047 #define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) 1048 1049 #define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ 1050 #define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ 1051 #define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) 1052 1053 #define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ 1054 #define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ 1055 #define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) 1056 1057 #define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ 1058 #define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ 1059 #define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) 1060 1061 #define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ 1062 #define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ 1063 #define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) 1064 1065 #define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ 1066 #define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ 1067 #define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) 1068 1069 #define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ 1070 #define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ 1071 #define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) 1072 1073 #define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ 1074 #define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ 1075 #define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) 1076 1077 /* ========== PIO definition for ICE peripheral ========== */ 1078 #define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ 1079 #define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) 1080 1081 #define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ 1082 #define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) 1083 1084 #define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ 1085 #define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) 1086 1087 #define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ 1088 #define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) 1089 1090 #define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ 1091 #define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) 1092 1093 #define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ 1094 #define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) 1095 1096 #define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ 1097 #define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) 1098 1099 /* ========== PIO definition for TPIU peripheral ========== */ 1100 #define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ 1101 #define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ 1102 #define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) 1103 1104 #define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ 1105 #define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ 1106 #define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) 1107 1108 #define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ 1109 #define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ 1110 #define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) 1111 1112 #define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ 1113 #define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ 1114 #define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) 1115 1116 #define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ 1117 #define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ 1118 #define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) 1119 1120 1121 #endif /* _SAMV71J19B_PIO_H_ */ 1122
